pluto_hdl_adi/library/xilinx/util_adxcvr/util_adxcvr_xch.v

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
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module util_adxcvr_xch #(
// parameters
parameter integer XCVR_TYPE = 0,
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4,
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parameter integer CPLL_FBDIV = 2,
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parameter integer CPLL_FBDIV_4_5 = 5,
parameter [15:0] CPLL_CFG0 = 16'b0000000111111010,
parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
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parameter [15:0] CH_HSPMUX = 16'b0010010000100100,
parameter integer PREIQ_FREQ_BST = 0,
parameter [15:0] RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] RXPI_CFG1 = 16'b0000000000010101,
parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,
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parameter integer TX_OUT_DIV = 1,
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parameter integer TX_CLK25_DIV = 20,
parameter integer TX_POLARITY = 0,
parameter [15:0] TX_PI_BIASSET = 1,
parameter [15:0] TXPI_CFG = 16'b0000000001010100,
parameter [15:0] A_TXDIFFCTRL = 5'b10110,
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parameter integer RX_OUT_DIV = 1,
parameter integer RX_CLK25_DIV = 20,
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parameter [15:0] RX_DFE_LPM_CFG = 16'h0104,
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parameter [31:0] RX_PMA_CFG = 32'h001e7080,
parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020,
parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,
parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001,
parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101,
parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100,
parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010,
parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010,
parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100,
parameter [15:0] RXDFE_KH_CFG2 = 16'h0200,
parameter [15:0] RXDFE_KH_CFG3 = 16'h4101,
parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00,
parameter [ 0:0] RX_XMODE_SEL = 1'b1,
parameter integer TXDRV_FREQBAND = 0,
parameter [15:0] TXFE_CFG0 = 16'b0000001111000010,
parameter [15:0] TXFE_CFG1 = 16'b0110110000000000,
parameter [15:0] TXFE_CFG2 = 16'b0110110000000000,
parameter [15:0] TXFE_CFG3 = 16'b0110110000000000,
parameter [15:0] TXPI_CFG0 = 16'b0000001100000000,
parameter [15:0] TXPI_CFG1 = 16'b0001000000000000,
parameter integer TXSWBST_EN = 0,
parameter integer RX_POLARITY = 0) (
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// pll interface
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input qpll2ch_clk,
input qpll2ch_ref_clk,
input qpll2ch_locked,
input qpll1_clk,
input qpll1_ref_clk,
input qpll1_locked,
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input cpll_ref_clk,
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input up_cpll_rst,
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// receive
input rx_p,
input rx_n,
output rx_out_clk,
output rx_out_clk_div2,
input rx_clk,
input rx_clk_2x,
output [DATA_PATH_WIDTH-1:0] rx_charisk,
output [DATA_PATH_WIDTH-1:0] rx_disperr,
output [DATA_PATH_WIDTH-1:0] rx_notintable,
output [DATA_PATH_WIDTH*8-1:0] rx_data,
input rx_calign,
output [1:0] rx_header,
output rx_block_sync,
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// transmit
output tx_p,
output tx_n,
output tx_out_clk,
output tx_out_clk_div2,
input tx_clk,
input tx_clk_2x,
input [DATA_PATH_WIDTH-1:0] tx_charisk,
input [DATA_PATH_WIDTH*8-1:0] tx_data,
input [1:0] tx_header,
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// up interface
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input up_rstn,
input up_clk,
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input up_es_enb,
input [11:0] up_es_addr,
input up_es_wr,
input [15:0] up_es_wdata,
output [15:0] up_es_rdata,
output up_es_ready,
input up_es_reset,
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output up_rx_pll_locked,
input up_rx_rst,
input up_rx_user_ready,
output up_rx_rst_done,
input [ 3:0] up_rx_prbssel,
input up_rx_prbscntreset,
output up_rx_prbserr,
output up_rx_prbslocked,
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input up_rx_lpm_dfe_n,
input [ 2:0] up_rx_rate,
input [ 1:0] up_rx_sys_clk_sel,
input [ 2:0] up_rx_out_clk_sel,
input up_rx_enb,
input [11:0] up_rx_addr,
input up_rx_wr,
input [15:0] up_rx_wdata,
output [15:0] up_rx_rdata,
output up_rx_ready,
output up_tx_pll_locked,
input up_tx_rst,
input up_tx_user_ready,
output up_tx_rst_done,
input up_tx_prbsforceerr,
input [ 3:0] up_tx_prbssel,
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input up_tx_lpm_dfe_n,
input [ 2:0] up_tx_rate,
input [ 1:0] up_tx_sys_clk_sel,
input [ 2:0] up_tx_out_clk_sel,
input [ 4:0] up_tx_diffctrl,
input [ 4:0] up_tx_postcursor,
input [ 4:0] up_tx_precursor,
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input up_tx_enb,
input [11:0] up_tx_addr,
input up_tx_wr,
input [15:0] up_tx_wdata,
output [15:0] up_tx_rdata,
output up_tx_ready
);
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localparam GTXE2_TRANSCEIVERS = 2;
localparam GTHE3_TRANSCEIVERS = 5;
localparam GTHE4_TRANSCEIVERS = 8;
localparam GTYE4_TRANSCEIVERS = 9;
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// internal registers
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reg [15:0] up_es_rdata_int = 'd0;
reg up_es_ready_int = 'd0;
reg [15:0] up_rx_rdata_int = 'd0;
reg up_rx_ready_int = 'd0;
reg [15:0] up_tx_rdata_int = 'd0;
reg up_tx_ready_int = 'd0;
reg [ 2:0] up_sel_int = 'd0;
reg up_enb_int = 'd0;
reg [11:0] up_addr_int = 'd0;
reg up_wr_int = 'd0;
reg [15:0] up_wdata_int = 'd0;
reg up_rx_rst_done_m1 = 'd0;
reg up_rx_rst_done_m2 = 'd0;
reg up_tx_rst_done_m1 = 'd0;
reg up_tx_rst_done_m2 = 'd0;
reg [ 2:0] rx_rate_m1 = 'd0;
reg [ 2:0] rx_rate_m2 = 'd0;
reg [ 2:0] tx_rate_m1 = 'd0;
reg [ 2:0] tx_rate_m2 = 'd0;
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// internal signals
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wire [15:0] up_rdata_s;
wire up_ready_s;
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wire [ 1:0] rx_sys_clk_sel_s;
wire rx_out_clk_s;
wire rx_rst_done_s;
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wire [ 1:0] tx_sys_clk_sel_s;
wire tx_out_clk_s;
wire tx_rst_done_s;
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wire [ 1:0] rx_pll_clk_sel_s;
wire [ 1:0] tx_pll_clk_sel_s;
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wire [11:0] rx_charisk_open_s;
wire [11:0] rx_disperr_open_s;
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wire [ 3:0] rx_notintable_open_s;
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wire [95:0] rx_data_open_s;
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wire cpll_locked_s;
wire rx_usrclk;
wire rx_usrclk2;
wire tx_usrclk;
wire tx_usrclk2;
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// pll
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assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : (up_rx_sys_clk_sel == 2'd2) ? qpll1_locked : cpll_locked_s;
assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : (up_tx_sys_clk_sel == 2'd2) ? qpll1_locked : cpll_locked_s;
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// drp access
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assign up_es_rdata = up_es_rdata_int;
assign up_es_ready = up_es_ready_int;
assign up_rx_rdata = up_rx_rdata_int;
assign up_rx_ready = up_rx_ready_int;
assign up_tx_rdata = up_tx_rdata_int;
assign up_tx_ready = up_tx_ready_int;
always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_es_rdata_int <= 15'd0;
up_es_ready_int <= 1'd0;
up_rx_rdata_int <= 15'd0;
up_rx_ready_int <= 1'd0;
up_tx_rdata_int <= 15'd0;
up_tx_ready_int <= 1'd0;
up_sel_int <= 3'd0;
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
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end else begin
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if (up_sel_int == 3'b100) begin
up_es_rdata_int <= up_rdata_s;
up_es_ready_int <= up_ready_s;
end else begin
up_es_rdata_int <= 15'd0;
up_es_ready_int <= 1'd0;
end
if (up_sel_int == 3'b101) begin
up_rx_rdata_int <= up_rdata_s;
up_rx_ready_int <= up_ready_s;
end else begin
up_rx_rdata_int <= 15'd0;
up_rx_ready_int <= 1'd0;
end
if (up_sel_int == 3'b110) begin
up_tx_rdata_int <= up_rdata_s;
up_tx_ready_int <= up_ready_s;
end else begin
up_tx_rdata_int <= 15'd0;
up_tx_ready_int <= 1'd0;
end
if (up_sel_int[2] == 1'b1) begin
if (up_ready_s == 1'b1) begin
up_sel_int <= 3'b000;
end
up_enb_int <= 1'b0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
end else if (up_es_enb == 1'b1) begin
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up_sel_int <= 3'b100;
up_enb_int <= 1'b1;
up_addr_int <= up_es_addr;
up_wr_int <= up_es_wr;
up_wdata_int <= up_es_wdata;
end else if (up_rx_enb == 1'b1) begin
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up_sel_int <= 3'b101;
up_enb_int <= 1'b1;
up_addr_int <= up_rx_addr;
up_wr_int <= up_rx_wr;
up_wdata_int <= up_rx_wdata;
end else if (up_tx_enb == 1'b1) begin
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up_sel_int <= 3'b110;
up_enb_int <= 1'b1;
up_addr_int <= up_tx_addr;
up_wr_int <= up_tx_wr;
up_wdata_int <= up_tx_wdata;
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end else begin
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up_sel_int <= 3'b000;
up_enb_int <= 1'b0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
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end
end
end
assign up_rx_rst_done = up_rx_rst_done_m2;
assign up_tx_rst_done = up_tx_rst_done_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rx_rst_done_m1 <= 'd0;
up_rx_rst_done_m2 <= 'd0;
up_tx_rst_done_m1 <= 'd0;
up_tx_rst_done_m2 <= 'd0;
end else begin
up_rx_rst_done_m1 <= rx_rst_done_s;
up_rx_rst_done_m2 <= up_rx_rst_done_m1;
up_tx_rst_done_m1 <= tx_rst_done_s;
up_tx_rst_done_m2 <= up_tx_rst_done_m1;
end
end
always @(posedge rx_clk) begin
rx_rate_m1 <= up_rx_rate;
rx_rate_m2 <= rx_rate_m1;
end
always @(posedge tx_clk) begin
tx_rate_m1 <= up_tx_rate;
tx_rate_m2 <= tx_rate_m1;
end
// Rx PRBS interface logic
wire rx_prbscntreset;
wire rx_prbserr;
wire rx_prbslocked;
wire [ 3:0] rx_prbssel;
reg rx_prbserr_sticky = 1'b0;
sync_bits #(.NUM_OF_BITS(5)) i_sync_bits_rx_prbs_in (
.in_bits ({up_rx_prbssel,
up_rx_prbscntreset}),
.out_resetn (1'b1),
.out_clk (rx_clk),
.out_bits ({rx_prbssel,
rx_prbscntreset})
);
always @(posedge rx_clk) begin
if (rx_prbscntreset) begin
rx_prbserr_sticky <= 1'b0;
end else if (rx_prbserr) begin
rx_prbserr_sticky <= 1'b1;
end
end
sync_bits #(.NUM_OF_BITS(2)) i_sync_bits_rx_prbs_out (
.in_bits ({rx_prbslocked,
rx_prbserr_sticky}),
.out_resetn (up_rstn),
.out_clk (up_clk),
.out_bits ({up_rx_prbslocked,
up_rx_prbserr})
);
// Tx PRBS interface logic
wire tx_prbsforceerr;
wire [ 3:0] tx_prbssel;
sync_bits #(.NUM_OF_BITS(5)) i_sync_bits_tx_prbs_in (
.in_bits ({up_tx_prbssel,
up_tx_prbsforceerr}),
.out_resetn (1'b1),
.out_clk (tx_clk),
.out_bits ({tx_prbssel,
tx_prbsforceerr})
);
// 204C specific logic
localparam ALIGN_COMMA_ENABLE = LINK_MODE[1] ? 10'b0000000000 : 10'b1111111111;
localparam ALIGN_MCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE";
localparam ALIGN_PCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE";
localparam CBCC_DATA_SOURCE_SEL = LINK_MODE[1] ? "ENCODED" : "DECODED";
localparam DEC_MCOMMA_DETECT = LINK_MODE[1] ? "FALSE" : "TRUE";
localparam DEC_PCOMMA_DETECT = LINK_MODE[1] ? "FALSE" : "TRUE";
localparam RXBUF_EN = LINK_MODE[1] ? "FALSE" : "TRUE";
localparam TXBUF_EN = LINK_MODE[1] ? "FALSE" : "TRUE";
localparam RX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40;
localparam TX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40;
localparam GEARBOX_MODE = LINK_MODE[1] ? 5'b10001 : 5'b00000;
localparam RXGEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE";
localparam TXGEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE";
localparam RX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1;
localparam TX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1;
localparam RX8B10BEN = LINK_MODE[1] ? 0 : 1;
localparam TX8B10BEN = LINK_MODE[1] ? 0 : 1;
localparam RXGBOX_FIFO_INIT_RD_ADDR = LINK_MODE[1] ? 3 : 4;
localparam RXBUF_THRESH_UNDFLW = LINK_MODE[1] ? 4 : 3;
wire [1:0] rx_header_s;
wire [127:0] rx_data_s;
wire [127:0] tx_data_s;
wire rx_bitslip_s;
assign rx_usrclk2 = rx_clk;
assign tx_usrclk2 = tx_clk;
generate
if (LINK_MODE[1]) begin
reg [3:0] rx_bitslip_d = 'h0;
reg rx_bitslip_req_s_d = 1'b0;
always @(posedge rx_clk) begin
rx_bitslip_d <= {rx_bitslip_d,rx_bitslip_s};
rx_bitslip_req_s_d <= rx_bitslip_req_s;
end
assign rx_bitslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
// Sync header alignment
sync_header_align i_sync_header_align (
.clk(rx_clk),
.reset(~rx_rst_done_s),
.i_data({rx_header_s,rx_data_s[63:0]}),
.i_slip(rx_bitslip_req_s),
.i_slip_done(rx_bitslip_d[3]),
.o_data(rx_data),
.o_header(rx_header),
.o_block_sync(rx_block_sync)
);
assign tx_data_s = {64'd0, tx_data};
assign rx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) ||
(XCVR_TYPE==GTHE4_TRANSCEIVERS) ? rx_clk_2x : rx_clk;
assign tx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) ||
(XCVR_TYPE==GTHE4_TRANSCEIVERS) ? tx_clk_2x : tx_clk;
end else begin
assign {rx_data_open_s, rx_data} = rx_data_s;
assign rx_bitslip_s = 1'b0;
assign tx_data_s = {96'd0, tx_data};
assign rx_usrclk = rx_clk;
assign tx_usrclk = tx_clk;
end
endgenerate
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// instantiations
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generate
if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
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end
endgenerate
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generate
if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
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assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
assign tx_sys_clk_sel_s = up_tx_sys_clk_sel;
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assign rx_pll_clk_sel_s = 2'd0;
assign tx_pll_clk_sel_s = 2'd0;
end
endgenerate
generate
if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
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GTXE2_CHANNEL #(
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
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.ALIGN_COMMA_WORD (4),
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.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
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.CHAN_BOND_MAX_SKEW (1),
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.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
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.CHAN_BOND_SEQ_LEN (1),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0000000000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG (24'h00001E),
.CPLL_LOCK_CFG (16'h01E8),
.CPLL_REFCLK_DIV (1),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DMONITOR_CFG (24'h000A00),
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.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'h000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (80'h00000000000000000000),
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.ES_QUAL_MASK (80'hffffffffffffffffffff),
.ES_SDATA_MASK (80'hffffffffff0000000000),
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.ES_VERT_OFFSET (9'b000000000),
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.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
.IS_CPLLLOCKDETCLK_INVERTED (1'b0),
.IS_DRPCLK_INVERTED (1'b0),
.IS_GTGREFCLK_INVERTED (1'b0),
.IS_RXUSRCLK2_INVERTED (1'b0),
.IS_RXUSRCLK_INVERTED (1'b0),
.IS_TXPHDLYTSTCLK_INVERTED (1'b0),
.IS_TXUSRCLK2_INVERTED (1'b0),
.IS_TXUSRCLK_INVERTED (1'b0),
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.OUTREFCLK_SEL_INV (2'b11),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD_ATTR (48'h000000000000),
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.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
.PMA_RSV (RX_PMA_CFG),
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.PMA_RSV2 (16'h2070),
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.PMA_RSV3 (2'b00),
.PMA_RSV4 (32'h00000000),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_ADDR_MODE ("FAST"),
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.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
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.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
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.RXCDR_CFG (RX_CDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
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.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXDFELPMRESET_TIME (7'b0001111),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (9'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXGEARBOX_EN ("FALSE"),
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.RXISCANRESET_TIME (5'b00001),
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.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RXOOB_CFG (7'b0000110),
.RXOUT_DIV (RX_OUT_DIV),
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.RXPCSRESET_TIME (5'b00001),
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.RXPHDLY_CFG (24'h084020),
.RXPH_CFG (24'h000000),
.RXPH_MONITOR_SEL (5'b00000),
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.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
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.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_BIAS_CFG (12'b000000000100),
.RX_BUFFER_CFG (6'b000000),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_PD (1'b1),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (3'b010),
.RX_DATA_WIDTH (40),
.RX_DDI_SEL (6'b000000),
.RX_DEBUG_CFG (12'b000000000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DFE_GAIN_CFG (23'h020FEA),
.RX_DFE_H2_CFG (12'b000000000000),
.RX_DFE_H3_CFG (12'b000001000000),
.RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_KL_CFG2 (32'h301148AC),
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.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
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.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
.RX_DFE_XYD_CFG (13'b0000000000000),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_INT_DATAWIDTH (1),
.RX_OS_CFG (13'b0000010000000),
.RX_SIG_VALID_DLY (10),
.RX_XCLK_SEL ("RXREC"),
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.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
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.SATA_BURST_SEQ_LEN (4'b0101),
.SATA_BURST_VAL (3'b111),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b111),
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.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
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.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_VERSION ("4.0"),
.TERM_RCAL_CFG (5'b10000),
.TERM_RCAL_OVRD (1'b0),
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.TRANS_TIME_RATE (8'h0E),
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.TST_RSV (32'h00000000),
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.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (9'h030),
.TXDLY_TAP_CFG (16'h0000),
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.TXGEARBOX_EN ("FALSE"),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00001),
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.TXPHDLY_CFG (24'h084020),
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.TXPH_CFG (16'h0780),
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.TXPH_MONITOR_SEL (5'b00000),
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.TXPMARESET_TIME (5'b00001),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_PD (1'b1),
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.TX_DATA_WIDTH (40),
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
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.TX_DRIVE_MODE ("DIRECT"),
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.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
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.TX_INT_DATAWIDTH (1),
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.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
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.TX_PREDRIVER_MODE (1'b0),
.TX_QPI_STATUS_EN (1'b0),
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.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
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.TX_XCLK_SEL ("TXOUT"),
.UCODEER_CLR (1'b0))
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i_gtxe2_channel (
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.RXOUTCLKPCS (),
.RXPHSLIPMONITOR (),
.PHYSTATUS (),
.RXCDRLOCK (),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCOMINITDET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXDATAVALID (),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXHEADERVALID (),
.RXPHALIGNDONE (),
.RXQPISENN (),
.RXQPISENP (),
.RXRATEDONE (),
.RXSTARTOFSEQ (),
.RXVALID (),
.TXCOMFINISH (),
.TXDLYSRESETDONE (),
.TXGEARBOXREADY (),
.TXPHALIGNDONE (),
.TXPHINITDONE (),
.TXQPISENN (),
.TXQPISENP (),
.TXRATEDONE (),
.PCSRSVDOUT (),
.RXCLKCORCNT (),
.RXHEADER (),
.RXCHBONDO (),
.RXPHMONITOR (),
.TSTOUT (),
.GTREFCLKMONITOR (),
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.CFGRESET (1'h0),
.CLKRSVD (4'h0),
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.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLLOCKDETCLK (up_clk),
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.CPLLLOCKEN (1'h1),
.CPLLPD (1'h0),
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.CPLLREFCLKLOST (),
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.CPLLREFCLKSEL (3'h1),
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.CPLLRESET (up_cpll_rst),
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.DMONITOROUT (),
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.DRPADDR (up_addr_int[8:0]),
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.DRPCLK (up_clk),
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.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPWE (up_wr_int),
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.EYESCANDATAERROR (),
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.EYESCANMODE (1'h0),
.EYESCANRESET (1'h0),
.EYESCANTRIGGER (1'h0),
.GTGREFCLK (1'h0),
.GTNORTHREFCLK0 (1'h0),
.GTNORTHREFCLK1 (1'h0),
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'h0),
.GTRESETSEL (1'h0),
.GTRSVD (16'h0),
.GTRXRESET (up_rx_rst),
.GTSOUTHREFCLK0 (1'h0),
.GTSOUTHREFCLK1 (1'h0),
.GTTXRESET (up_tx_rst),
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.GTXRXN (rx_n),
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.GTXRXP (rx_p),
.GTXTXN (tx_n),
.GTXTXP (tx_p),
.LOOPBACK (3'h0),
.PCSRSVDIN (16'h0),
.PCSRSVDIN2 (5'h0),
.PMARSVDIN (5'h0),
.PMARSVDIN2 (5'h0),
.QPLLCLK (qpll2ch_clk),
.QPLLREFCLK (qpll2ch_ref_clk),
.RESETOVRD (1'h0),
.RX8B10BEN (1'h1),
.RXBUFRESET (1'h0),
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.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
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.RXCDRFREQRESET (1'h0),
.RXCDRHOLD (1'h0),
.RXCDROVRDEN (1'h0),
.RXCDRRESET (1'h0),
.RXCDRRESETRSV (1'h0),
.RXCHARISCOMMA (),
.RXCHARISK ({rx_charisk_open_s[3:0], rx_charisk}),
.RXCHBONDEN (1'h0),
.RXCHBONDI (5'h0),
.RXCHBONDLEVEL (3'h0),
.RXCHBONDMASTER (1'h1),
.RXCHBONDSLAVE (1'h0),
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.RXCOMMADET (),
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.RXCOMMADETEN (1'h1),
.RXDATA ({rx_data_open_s[31:0], rx_data}),
.RXDDIEN (1'h0),
.RXDFEAGCHOLD (1'h0),
.RXDFEAGCOVRDEN (1'h0),
.RXDFECM1EN (1'h0),
.RXDFELFHOLD (1'h0),
.RXDFELFOVRDEN (1'h0),
.RXDFELPMRESET (1'h0),
.RXDFETAP2HOLD (1'h0),
.RXDFETAP2OVRDEN (1'h0),
.RXDFETAP3HOLD (1'h0),
.RXDFETAP3OVRDEN (1'h0),
.RXDFETAP4HOLD (1'h0),
.RXDFETAP4OVRDEN (1'h0),
.RXDFETAP5HOLD (1'h0),
.RXDFETAP5OVRDEN (1'h0),
.RXDFEUTHOLD (1'h0),
.RXDFEUTOVRDEN (1'h0),
.RXDFEVPHOLD (1'h0),
.RXDFEVPOVRDEN (1'h0),
.RXDFEVSEN (1'h0),
.RXDFEXYDEN (1'h1),
.RXDFEXYDHOLD (1'h0),
.RXDFEXYDOVRDEN (1'h0),
.RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}),
.RXDLYBYPASS (1'h1),
.RXDLYEN (1'h0),
.RXDLYOVRDEN (1'h0),
.RXDLYSRESET (1'h0),
.RXELECIDLEMODE (2'h3),
.RXGEARBOXSLIP (1'h0),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMHFHOLD (1'h0),
.RXLPMHFOVRDEN (1'h0),
.RXLPMLFHOLD (1'h0),
.RXLPMLFKLOVRDEN (1'h0),
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.RXMCOMMAALIGNEN (rx_calign),
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.RXMONITOROUT (),
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.RXMONITORSEL (2'h0),
.RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
.RXOOBRESET (1'h0),
.RXOSHOLD (1'h0),
.RXOSOVRDEN (1'h0),
.RXOUTCLK (rx_out_clk_s),
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.RXOUTCLKFABRIC (),
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.RXOUTCLKSEL (up_rx_out_clk_sel),
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.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'h0),
.RXPD (2'h0),
.RXPHALIGN (1'h0),
.RXPHALIGNEN (1'h0),
.RXPHDLYPD (1'h0),
.RXPHDLYRESET (1'h0),
.RXPHOVRDEN (1'h0),
.RXPMARESET (1'h0),
.RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSERR (rx_prbserr),
.RXPRBSSEL (rx_prbssel[2:0]),
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.RXQPIEN (1'h0),
.RXRATE (rx_rate_m2),
.RXRESETDONE (rx_rst_done_s),
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.RXSLIDE (1'h0),
.RXSTATUS (),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_usrclk),
.RXUSRCLK2 (rx_usrclk2),
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.SETERRSTATUS (1'h0),
.TSTIN (20'hfffff),
.TX8B10BBYPASS (8'h0),
.TX8B10BEN (1'h1),
.TXBUFDIFFCTRL (3'h4),
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.TXBUFSTATUS (),
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.TXCHARDISPMODE (8'h0),
.TXCHARDISPVAL (8'h0),
.TXCHARISK ({4'd0, tx_charisk}),
.TXCOMINIT (1'h0),
.TXCOMSAS (1'h0),
.TXCOMWAKE (1'h0),
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.TXDATA ({32'd0, tx_data}),
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.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
.TXDIFFCTRL (up_tx_diffctrl[3:0]),
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.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
.TXDLYHOLD (1'h0),
.TXDLYOVRDEN (1'h0),
.TXDLYSRESET (1'h0),
.TXDLYUPDOWN (1'h0),
.TXELECIDLE (1'h0),
.TXHEADER (3'h0),
.TXINHIBIT (1'h0),
.TXMAINCURSOR (7'h0),
.TXMARGIN (3'h0),
.TXOUTCLK (tx_out_clk_s),
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.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
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.TXOUTCLKSEL (up_tx_out_clk_sel),
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.TXPCSRESET (1'h0),
.TXPD (2'h0),
.TXPDELECIDLEMODE (1'h0),
.TXPHALIGN (1'h0),
.TXPHALIGNEN (1'h0),
.TXPHDLYPD (1'h0),
.TXPHDLYRESET (1'h0),
.TXPHDLYTSTCLK (1'h0),
.TXPHINIT (1'h0),
.TXPHOVRDEN (1'h0),
.TXPISOPD (1'h0),
.TXPMARESET (1'h0),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor),
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.TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (tx_prbssel[2:0]),
.TXPRECURSOR (up_tx_precursor),
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.TXPRECURSORINV (1'h0),
.TXQPIBIASEN (1'h0),
.TXQPISTRONGPDOWN (1'h0),
.TXQPIWEAKPUP (1'h0),
.TXRATE (tx_rate_m2),
.TXRESETDONE (tx_rst_done_s),
.TXSEQUENCE (7'h0),
.TXSTARTSEQ (1'h0),
.TXSWING (1'h0),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_usrclk),
.TXUSRCLK2 (tx_usrclk2));
// Emulate PRBS lock
assign rx_prbslocked = ~rx_prbserr_sticky;
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end
endgenerate
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generate
if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin
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BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
BUFG_GT i_rx_div2_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd1),
.I (rx_out_clk_s),
.O (rx_out_clk_div2));
BUFG_GT i_tx_div2_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd1),
.I (tx_out_clk_s),
.O (tx_out_clk_div2));
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end
endgenerate
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generate
if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]};
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]};
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assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
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end
endgenerate
generate
if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin
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GTHE3_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
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.ADAPT_CFG0 (16'hf800),
.ADAPT_CFG1 (16'h0000),
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.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
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.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
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.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
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.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_TXPROGDIVRESET (1'b0),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
2016-06-14 16:18:56 +00:00
.CDR_SWAP_MODE_EN (1'b0),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
2016-10-19 17:05:59 +00:00
.CHAN_BOND_MAX_SKEW (1),
2016-06-14 16:18:56 +00:00
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
2016-10-19 17:05:59 +00:00
.CHAN_BOND_SEQ_LEN (1),
2016-06-14 16:18:56 +00:00
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
2016-10-19 17:05:59 +00:00
.CLK_COR_REPEAT_WAIT (0),
2016-06-14 16:18:56 +00:00
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
2016-10-19 17:05:59 +00:00
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3[5:0]),
2016-06-14 16:18:56 +00:00
.CPLL_FBDIV (CPLL_FBDIV),
2016-10-19 17:05:59 +00:00
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'h02b2),
.CPLL_INIT_CFG1 (8'h00),
.CPLL_LOCK_CFG (16'h01e8),
.CPLL_REFCLK_DIV (1),
2016-06-14 16:18:56 +00:00
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
2016-06-14 16:18:56 +00:00
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DFE_D_X_REL_POS (1'b0),
.DFE_VCM_COMP_EN (1'b0),
2016-10-19 17:05:59 +00:00
.DMONITOR_CFG0 (10'h000),
.DMONITOR_CFG1 (8'h00),
2016-06-14 16:18:56 +00:00
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
2016-10-19 17:05:59 +00:00
.ES_HORZ_OFFSET (12'h000),
2016-06-14 16:18:56 +00:00
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
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.ES_QUALIFIER0 (16'h0000),
.ES_QUALIFIER1 (16'h0000),
.ES_QUALIFIER2 (16'h0000),
.ES_QUALIFIER3 (16'h0000),
.ES_QUALIFIER4 (16'h0000),
.ES_QUAL_MASK0 (16'hffff),
.ES_QUAL_MASK1 (16'hffff),
.ES_QUAL_MASK2 (16'hffff),
.ES_QUAL_MASK3 (16'hffff),
.ES_QUAL_MASK4 (16'hffff),
2016-10-19 17:05:59 +00:00
.ES_SDATA_MASK0 (16'h0000),
.ES_SDATA_MASK1 (16'h0000),
2017-08-08 15:03:38 +00:00
.ES_SDATA_MASK2 (16'hff00),
.ES_SDATA_MASK3 (16'hffff),
.ES_SDATA_MASK4 (16'hffff),
2016-06-14 16:18:56 +00:00
.EVODD_PHI_CFG (11'b00000000000),
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (GEARBOX_MODE),
2016-06-14 16:18:56 +00:00
.GM_BIAS_SELECT (1'b0),
.LOCAL_MASTER (1'b1),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
2016-10-19 17:05:59 +00:00
.PCIE_BUFG_DIV_CTRL (16'h1000),
.PCIE_RXPCS_CFG_GEN3 (16'h02a4),
.PCIE_RXPMA_CFG (16'h000a),
.PCIE_TXPCS_CFG_GEN3 (16'h24a4),
.PCIE_TXPMA_CFG (16'h000a),
2016-06-14 16:18:56 +00:00
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
.PCS_RSVD1 (3'b000),
2016-10-19 17:05:59 +00:00
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h19),
.PD_TRANS_TIME_TO_P2 (8'h64),
.PLL_SEL_MODE_GEN12 (2'h3),
.PLL_SEL_MODE_GEN3 (2'h3),
.PMA_RSV1 (16'hf000),
2016-06-14 16:18:56 +00:00
.PROCESS_PAR (3'b010),
2016-10-19 17:05:59 +00:00
.RATE_SW_USE_DRP (1'b1),
2016-06-14 16:18:56 +00:00
.RESET_POWERSAVE_DISABLE (1'b0),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN (RXBUF_EN),
2016-06-14 16:18:56 +00:00
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
2016-10-19 17:05:59 +00:00
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
2016-06-14 16:18:56 +00:00
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
2016-06-14 16:18:56 +00:00
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
2016-10-19 17:05:59 +00:00
.RXCDR_CFG0 (16'h0000),
.RXCDR_CFG0_GEN3 (16'h0000),
.RXCDR_CFG1 (16'h0000),
.RXCDR_CFG1_GEN3 (16'h0000),
.RXCDR_CFG2 (16'h0766),
.RXCDR_CFG2_GEN3 (16'h07e6),
.RXCDR_CFG3 (16'h0000),
.RXCDR_CFG3_GEN3 (16'h0000),
.RXCDR_CFG4 (16'h0000),
.RXCDR_CFG4_GEN3 (16'h0000),
.RXCDR_CFG5 (16'h0000),
.RXCDR_CFG5_GEN3 (16'h0000),
2016-06-14 16:18:56 +00:00
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
2016-10-19 17:05:59 +00:00
.RXCDR_LOCK_CFG0 (16'h4480),
.RXCDR_LOCK_CFG1 (16'h5fff),
.RXCDR_LOCK_CFG2 (16'h77c3),
2016-06-14 16:18:56 +00:00
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
2016-10-19 17:05:59 +00:00
.RXCFOK_CFG0 (16'h4000),
.RXCFOK_CFG1 (16'h0065),
.RXCFOK_CFG2 (16'h002e),
2016-06-14 16:18:56 +00:00
.RXDFELPMRESET_TIME (7'b0001111),
2016-10-19 17:05:59 +00:00
.RXDFELPM_KL_CFG0 (16'h0000),
.RXDFELPM_KL_CFG1 (16'h0032),
.RXDFELPM_KL_CFG2 (16'h0000),
.RXDFE_CFG0 (16'h0a00),
.RXDFE_CFG1 (16'h0000),
.RXDFE_GC_CFG0 (16'h0000),
.RXDFE_GC_CFG1 (16'h7870),
.RXDFE_GC_CFG2 (16'h0000),
.RXDFE_H2_CFG0 (16'h0000),
.RXDFE_H2_CFG1 (16'h0000),
.RXDFE_H3_CFG0 (16'h4000),
.RXDFE_H3_CFG1 (16'h0000),
.RXDFE_H4_CFG0 (16'h2000),
.RXDFE_H4_CFG1 (16'h0003),
.RXDFE_H5_CFG0 (16'h2000),
.RXDFE_H5_CFG1 (16'h0003),
.RXDFE_H6_CFG0 (16'h2000),
.RXDFE_H6_CFG1 (16'h0000),
.RXDFE_H7_CFG0 (16'h2000),
.RXDFE_H7_CFG1 (16'h0000),
.RXDFE_H8_CFG0 (16'h2000),
.RXDFE_H8_CFG1 (16'h0000),
.RXDFE_H9_CFG0 (16'h2000),
.RXDFE_H9_CFG1 (16'h0000),
.RXDFE_HA_CFG0 (16'h2000),
.RXDFE_HA_CFG1 (16'h0000),
.RXDFE_HB_CFG0 (16'h2000),
.RXDFE_HB_CFG1 (16'h0000),
.RXDFE_HC_CFG0 (16'h0000),
.RXDFE_HC_CFG1 (16'h0000),
.RXDFE_HD_CFG0 (16'h0000),
.RXDFE_HD_CFG1 (16'h0000),
.RXDFE_HE_CFG0 (16'h0000),
.RXDFE_HE_CFG1 (16'h0000),
.RXDFE_HF_CFG0 (16'h0000),
.RXDFE_HF_CFG1 (16'h0000),
.RXDFE_OS_CFG0 (16'h8000),
.RXDFE_OS_CFG1 (16'h0000),
.RXDFE_UT_CFG0 (16'h8000),
.RXDFE_UT_CFG1 (16'h0003),
.RXDFE_VP_CFG0 (16'haa00),
.RXDFE_VP_CFG1 (16'h0033),
.RXDLY_CFG (16'h001f),
.RXDLY_LCFG (16'h0030),
2016-06-14 16:18:56 +00:00
.RXELECIDLE_CFG ("Sigcfg_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
.RXGEARBOX_EN (RXGEARBOX_EN),
2016-06-14 16:18:56 +00:00
.RXISCANRESET_TIME (5'b00001),
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.RXLPM_CFG (16'h0000),
.RXLPM_GC_CFG (16'h1000),
.RXLPM_KH_CFG0 (16'h0000),
.RXLPM_KH_CFG1 (16'h0002),
.RXLPM_OS_CFG0 (16'h8000),
.RXLPM_OS_CFG1 (16'h0002),
2016-06-14 16:18:56 +00:00
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
2016-10-19 17:05:59 +00:00
.RXPHBEACON_CFG (16'h0000),
.RXPHDLY_CFG (16'h2020),
.RXPHSAMP_CFG (16'h2100),
.RXPHSLIP_CFG (16'h6622),
2016-06-14 16:18:56 +00:00
.RXPH_MONITOR_SEL (5'b00000),
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.RXPI_CFG0 (2'b01),
.RXPI_CFG1 (2'b01),
.RXPI_CFG2 (2'b01),
.RXPI_CFG3 (2'b01),
2016-06-14 16:18:56 +00:00
.RXPI_CFG4 (1'b0),
.RXPI_CFG5 (1'b1),
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.RXPI_CFG6 (3'b011),
2016-06-14 16:18:56 +00:00
.RXPI_LPM (1'b0),
.RXPI_VREFSEL (1'b0),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
2016-10-19 17:05:59 +00:00
.RX_BIAS_CFG0 (16'h0ab4),
2016-06-14 16:18:56 +00:00
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (4'b1010),
.RX_CTLE3_LPF (8'b00000001),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
2016-06-14 16:18:56 +00:00
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DFELPM_CFG0 (4'b0110),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG0 (2'b10),
2016-10-19 17:05:59 +00:00
.RX_DFE_AGC_CFG1 (3'b000),
2016-06-14 16:18:56 +00:00
.RX_DFE_KL_LPM_KH_CFG0 (2'b01),
2016-10-19 17:05:59 +00:00
.RX_DFE_KL_LPM_KH_CFG1 (3'b000),
2016-06-14 16:18:56 +00:00
.RX_DFE_KL_LPM_KL_CFG0 (2'b01),
2016-10-19 17:05:59 +00:00
.RX_DFE_KL_LPM_KL_CFG1 (3'b000),
2016-06-14 16:18:56 +00:00
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_HI_LR (1'b1),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b00),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
2016-10-19 17:05:59 +00:00
.RX_INT_DATAWIDTH (1),
2016-06-14 16:18:56 +00:00
.RX_PMA_POWER_SAVE (1'b0),
2016-10-19 17:05:59 +00:00
.RX_PROGDIV_CFG (0.000000),
.RX_SAMPLE_PERIOD (3'b111),
2016-06-14 16:18:56 +00:00
.RX_SIG_VALID_DLY (11),
.RX_SUM_DFETAPREP_EN (1'b0),
2016-10-19 17:05:59 +00:00
.RX_SUM_IREF_TUNE (4'b1100),
.RX_SUM_RES_CTRL (2'b11),
2016-06-14 16:18:56 +00:00
.RX_SUM_VCMTUNE (4'b0000),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b000),
.RX_TUNE_AFE_OS (2'b10),
.RX_WIDEMODE_CDR (1'b1),
.RX_XCLK_SEL ("RXDES"),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
2016-10-19 17:05:59 +00:00
.SATA_BURST_SEQ_LEN (4'b1110),
2016-06-14 16:18:56 +00:00
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.SHOW_REALIGN_COMMA ("TRUE"),
2016-10-19 17:05:59 +00:00
.SIM_MODE ("FAST"),
2016-06-14 16:18:56 +00:00
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL (1'b0),
.SIM_VERSION (2),
2016-10-19 17:05:59 +00:00
.TAPDLY_SET_TX (2'h0),
2016-06-14 16:18:56 +00:00
.TEMPERATUR_PAR (4'b0010),
.TERM_RCAL_CFG (15'b100001000010000),
.TERM_RCAL_OVRD (3'b000),
2016-10-19 17:05:59 +00:00
.TRANS_TIME_RATE (8'h0e),
.TST_RSV0 (8'h00),
.TST_RSV1 (8'h00),
.TXBUF_EN (TXBUF_EN),
2016-06-14 16:18:56 +00:00
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
2016-10-19 17:05:59 +00:00
.TXDLY_CFG (16'h0009),
.TXDLY_LCFG (16'h0050),
2016-06-14 16:18:56 +00:00
.TXDRVBIAS_N (4'b1010),
.TXDRVBIAS_P (4'b1010),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN (TXGEARBOX_EN),
2016-06-14 16:18:56 +00:00
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
2016-10-19 17:05:59 +00:00
.TXPHDLY_CFG0 (16'h2020),
.TXPHDLY_CFG1 (16'h0075),
.TXPH_CFG (16'h0980),
2016-06-14 16:18:56 +00:00
.TXPH_MONITOR_SEL (5'b00000),
2016-10-19 17:05:59 +00:00
.TXPI_CFG0 (2'b01),
.TXPI_CFG1 (2'b01),
.TXPI_CFG2 (2'b01),
2016-06-14 16:18:56 +00:00
.TXPI_CFG3 (1'b0),
.TXPI_CFG4 (1'b1),
2016-10-19 17:05:59 +00:00
.TXPI_CFG5 (3'b011),
2016-06-14 16:18:56 +00:00
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_LPM (1'b0),
.TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.TXPI_PPM_CFG (8'b00000000),
2016-10-19 17:05:59 +00:00
.TXPI_SYNFREQ_PPM (3'b001),
2016-06-14 16:18:56 +00:00
.TXPI_VREFSEL (1'b0),
.TXPMARESET_TIME (5'b00011),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
2016-06-14 16:18:56 +00:00
.TX_DCD_CFG (6'b000010),
.TX_DCD_EN (1'b0),
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_EML_PHI_TUNE (1'b0),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
2016-10-19 17:05:59 +00:00
.TX_INT_DATAWIDTH (1),
2016-06-14 16:18:56 +00:00
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1001111),
.TX_MARGIN_FULL_1 (7'b1001110),
.TX_MARGIN_FULL_2 (7'b1001100),
.TX_MARGIN_FULL_3 (7'b1001010),
.TX_MARGIN_FULL_4 (7'b1001000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000101),
.TX_MARGIN_LOW_2 (7'b1000011),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
.TX_MODE_SEL (3'b000),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
.TX_PROGCLK_SEL ("PREPI"),
2016-10-19 17:05:59 +00:00
.TX_PROGDIV_CFG (0.000000),
2016-06-14 16:18:56 +00:00
.TX_QPI_STATUS_EN (1'b0),
2016-10-19 17:05:59 +00:00
.TX_RXDETECT_CFG (14'h0032),
2016-06-14 16:18:56 +00:00
.TX_RXDETECT_REF (3'b100),
2016-10-19 17:05:59 +00:00
.TX_SAMPLE_PERIOD (3'b111),
.TX_SARC_LPBK_ENB (1'b0),
.TX_XCLK_SEL ("TXOUT"),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.WB_MODE (2'b00))
i_gthe3_channel (
2016-06-14 16:18:56 +00:00
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
2016-10-19 17:05:59 +00:00
.CFGRESET (1'h0),
.CLKRSVD0 (1'h0),
.CLKRSVD1 (1'h0),
2016-06-14 16:18:56 +00:00
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
2016-10-19 17:05:59 +00:00
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'h1),
.CPLLPD (1'h0),
2016-06-14 16:18:56 +00:00
.CPLLREFCLKLOST (),
2016-10-19 17:05:59 +00:00
.CPLLREFCLKSEL (3'h1),
.CPLLRESET (up_cpll_rst),
.DMONFIFORESET (1'h0),
.DMONITORCLK (1'h0),
2016-06-14 16:18:56 +00:00
.DMONITOROUT (),
2016-10-19 17:05:59 +00:00
.DRPADDR (up_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
2016-06-17 15:59:42 +00:00
.DRPDO (up_rdata_s),
2016-10-19 17:05:59 +00:00
.DRPEN (up_enb_int),
2016-06-17 15:59:42 +00:00
.DRPRDY (up_ready_s),
2016-10-19 17:05:59 +00:00
.DRPWE (up_wr_int),
.EVODDPHICALDONE (1'h0),
.EVODDPHICALSTART (1'h0),
.EVODDPHIDRDEN (1'h0),
.EVODDPHIDWREN (1'h0),
.EVODDPHIXRDEN (1'h0),
.EVODDPHIXWREN (1'h0),
2016-06-14 16:18:56 +00:00
.EYESCANDATAERROR (),
2016-10-19 17:05:59 +00:00
.EYESCANMODE (1'h0),
.EYESCANRESET (1'h0),
.EYESCANTRIGGER (1'h0),
.GTGREFCLK (1'h0),
.GTHRXN (rx_n),
.GTHRXP (rx_p),
2016-06-14 16:18:56 +00:00
.GTHTXN (tx_n),
.GTHTXP (tx_p),
2016-10-19 17:05:59 +00:00
.GTNORTHREFCLK0 (1'h0),
.GTNORTHREFCLK1 (1'h0),
2016-06-14 16:18:56 +00:00
.GTPOWERGOOD (),
2016-10-19 17:05:59 +00:00
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'h0),
2016-06-14 16:18:56 +00:00
.GTREFCLKMONITOR (),
2016-10-19 17:05:59 +00:00
.GTRESETSEL (1'h0),
.GTRSVD (16'h0),
.GTRXRESET (up_rx_rst),
.GTSOUTHREFCLK0 (1'h0),
.GTSOUTHREFCLK1 (1'h0),
.GTTXRESET (up_tx_rst),
.LOOPBACK (3'h0),
.LPBKRXTXSEREN (1'h0),
.LPBKTXRXSEREN (1'h0),
.PCIEEQRXEQADAPTDONE (1'h0),
2016-06-14 16:18:56 +00:00
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
2016-10-19 17:05:59 +00:00
.PCIERSTIDLE (1'h0),
.PCIERSTTXSYNCSTART (1'h0),
2016-06-14 16:18:56 +00:00
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
2016-10-19 17:05:59 +00:00
.PCIEUSERRATEDONE (1'h0),
2016-06-14 16:18:56 +00:00
.PCIEUSERRATESTART (),
2016-10-19 17:05:59 +00:00
.PCSRSVDIN (16'h0),
.PCSRSVDIN2 (5'h0),
2016-06-14 16:18:56 +00:00
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
2016-10-19 17:05:59 +00:00
.PMARSVDIN (5'h0),
.QPLL0CLK (qpll2ch_clk),
.QPLL0REFCLK (qpll2ch_ref_clk),
.QPLL1CLK (qpll1_clk),
.QPLL1REFCLK (qpll1_ref_clk),
2016-06-14 16:18:56 +00:00
.RESETEXCEPTION (),
2016-10-19 17:05:59 +00:00
.RESETOVRD (1'h0),
.RSTCLKENTX (1'h0),
.RX8B10BEN (RX8B10BEN),
2016-10-19 17:05:59 +00:00
.RXBUFRESET (1'h0),
2016-06-14 16:18:56 +00:00
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
2016-10-19 17:05:59 +00:00
.RXCDRFREQRESET (1'h0),
.RXCDRHOLD (1'h0),
2016-06-14 16:18:56 +00:00
.RXCDRLOCK (),
2016-10-19 17:05:59 +00:00
.RXCDROVRDEN (1'h0),
2016-06-14 16:18:56 +00:00
.RXCDRPHDONE (),
2016-10-19 17:05:59 +00:00
.RXCDRRESET (1'h0),
.RXCDRRESETRSV (1'h0),
2016-06-14 16:18:56 +00:00
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
2016-10-19 17:05:59 +00:00
.RXCHBONDEN (1'h0),
.RXCHBONDI (5'h0),
.RXCHBONDLEVEL (3'h0),
.RXCHBONDMASTER (1'h0),
2016-06-14 16:18:56 +00:00
.RXCHBONDO (),
2016-10-19 17:05:59 +00:00
.RXCHBONDSLAVE (1'h0),
2016-06-14 16:18:56 +00:00
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
2016-10-19 17:05:59 +00:00
.RXCOMMADETEN (1'h1),
2016-06-14 16:18:56 +00:00
.RXCOMSASDET (),
.RXCOMWAKEDET (),
2016-06-17 15:59:42 +00:00
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
2016-06-14 16:18:56 +00:00
.RXCTRL2 (),
2016-06-17 15:59:42 +00:00
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA (rx_data_s),
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.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
2016-10-19 17:05:59 +00:00
.RXDFEAGCCTRL (2'h1),
.RXDFEAGCHOLD (1'h0),
.RXDFEAGCOVRDEN (1'h0),
.RXDFELFHOLD (1'h0),
.RXDFELFOVRDEN (1'h0),
.RXDFELPMRESET (1'h0),
.RXDFETAP10HOLD (1'h0),
.RXDFETAP10OVRDEN (1'h0),
.RXDFETAP11HOLD (1'h0),
.RXDFETAP11OVRDEN (1'h0),
.RXDFETAP12HOLD (1'h0),
.RXDFETAP12OVRDEN (1'h0),
.RXDFETAP13HOLD (1'h0),
.RXDFETAP13OVRDEN (1'h0),
.RXDFETAP14HOLD (1'h0),
.RXDFETAP14OVRDEN (1'h0),
.RXDFETAP15HOLD (1'h0),
.RXDFETAP15OVRDEN (1'h0),
.RXDFETAP2HOLD (1'h0),
.RXDFETAP2OVRDEN (1'h0),
.RXDFETAP3HOLD (1'h0),
.RXDFETAP3OVRDEN (1'h0),
.RXDFETAP4HOLD (1'h0),
.RXDFETAP4OVRDEN (1'h0),
.RXDFETAP5HOLD (1'h0),
.RXDFETAP5OVRDEN (1'h0),
.RXDFETAP6HOLD (1'h0),
.RXDFETAP6OVRDEN (1'h0),
.RXDFETAP7HOLD (1'h0),
.RXDFETAP7OVRDEN (1'h0),
.RXDFETAP8HOLD (1'h0),
.RXDFETAP8OVRDEN (1'h0),
.RXDFETAP9HOLD (1'h0),
.RXDFETAP9OVRDEN (1'h0),
.RXDFEUTHOLD (1'h0),
.RXDFEUTOVRDEN (1'h0),
.RXDFEVPHOLD (1'h0),
.RXDFEVPOVRDEN (1'h0),
.RXDFEVSEN (1'h0),
.RXDFEXYDEN (1'h1),
.RXDLYBYPASS (1'h1),
.RXDLYEN (1'h0),
.RXDLYOVRDEN (1'h0),
.RXDLYSRESET (1'h0),
2016-06-14 16:18:56 +00:00
.RXDLYSRESETDONE (),
.RXELECIDLE (),
2016-10-19 17:05:59 +00:00
.RXELECIDLEMODE (2'h3),
.RXGEARBOXSLIP (rx_bitslip_s),
.RXHEADER (rx_header_s),
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.RXHEADERVALID (),
2016-10-19 17:05:59 +00:00
.RXLATCLK (1'h0),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMGCHOLD (1'h0),
.RXLPMGCOVRDEN (1'h0),
.RXLPMHFHOLD (1'h0),
.RXLPMHFOVRDEN (1'h0),
.RXLPMLFHOLD (1'h0),
.RXLPMLFKLOVRDEN (1'h0),
.RXLPMOSHOLD (1'h0),
.RXLPMOSOVRDEN (1'h0),
.RXMCOMMAALIGNEN (rx_calign),
2016-06-14 16:18:56 +00:00
.RXMONITOROUT (),
2016-10-19 17:05:59 +00:00
.RXMONITORSEL (2'h0),
.RXOOBRESET (1'h0),
.RXOSCALRESET (1'h0),
.RXOSHOLD (1'h0),
.RXOSINTCFG (4'hd),
2016-06-14 16:18:56 +00:00
.RXOSINTDONE (),
2016-10-19 17:05:59 +00:00
.RXOSINTEN (1'h1),
.RXOSINTHOLD (1'h0),
.RXOSINTOVRDEN (1'h0),
2016-06-14 16:18:56 +00:00
.RXOSINTSTARTED (),
2016-10-19 17:05:59 +00:00
.RXOSINTSTROBE (1'h0),
2016-06-14 16:18:56 +00:00
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
2016-10-19 17:05:59 +00:00
.RXOSINTTESTOVRDEN (1'h0),
.RXOSOVRDEN (1'h0),
.RXOUTCLK (rx_out_clk_s),
2016-06-14 16:18:56 +00:00
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
2016-10-19 17:05:59 +00:00
.RXOUTCLKSEL (up_rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'h0),
.RXPD (2'h0),
.RXPHALIGN (1'h0),
2016-06-14 16:18:56 +00:00
.RXPHALIGNDONE (),
2016-10-19 17:05:59 +00:00
.RXPHALIGNEN (1'h0),
2016-06-14 16:18:56 +00:00
.RXPHALIGNERR (),
2016-10-19 17:05:59 +00:00
.RXPHDLYPD (1'h1),
.RXPHDLYRESET (1'h0),
.RXPHOVRDEN (1'h0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'h0),
2016-06-14 16:18:56 +00:00
.RXPMARESETDONE (),
.RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSERR (rx_prbserr),
.RXPRBSLOCKED (rx_prbslocked),
.RXPRBSSEL (rx_prbssel),
2016-06-14 16:18:56 +00:00
.RXPRGDIVRESETDONE (),
2021-05-18 10:26:43 +00:00
.RXPROGDIVRESET (up_rx_rst),
2016-10-19 17:05:59 +00:00
.RXQPIEN (1'h0),
2016-06-14 16:18:56 +00:00
.RXQPISENN (),
.RXQPISENP (),
2016-10-19 17:05:59 +00:00
.RXRATE (rx_rate_m2),
2016-06-14 16:18:56 +00:00
.RXRATEDONE (),
2016-10-19 17:05:59 +00:00
.RXRATEMODE (1'h0),
2016-06-14 16:18:56 +00:00
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done_s),
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.RXSLIDE (1'h0),
2016-06-14 16:18:56 +00:00
.RXSLIDERDY (),
.RXSLIPDONE (),
2016-10-19 17:05:59 +00:00
.RXSLIPOUTCLK (1'h0),
2016-06-14 16:18:56 +00:00
.RXSLIPOUTCLKRDY (),
2016-10-19 17:05:59 +00:00
.RXSLIPPMA (1'h0),
2016-06-14 16:18:56 +00:00
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
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.RXSYNCALLIN (1'h0),
2016-06-14 16:18:56 +00:00
.RXSYNCDONE (),
2016-10-19 17:05:59 +00:00
.RXSYNCIN (1'h0),
.RXSYNCMODE (1'h0),
2016-06-14 16:18:56 +00:00
.RXSYNCOUT (),
2016-10-19 17:05:59 +00:00
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_usrclk),
.RXUSRCLK2 (rx_usrclk2),
2016-06-14 16:18:56 +00:00
.RXVALID (),
2016-10-19 17:05:59 +00:00
.SIGVALIDCLK (1'h0),
.TSTIN (20'h0),
.TX8B10BBYPASS (8'h0),
.TX8B10BEN (TX8B10BEN),
2016-10-19 17:05:59 +00:00
.TXBUFDIFFCTRL (3'h0),
2016-06-14 16:18:56 +00:00
.TXBUFSTATUS (),
.TXCOMFINISH (),
2016-10-19 17:05:59 +00:00
.TXCOMINIT (1'h0),
.TXCOMSAS (1'h0),
.TXCOMWAKE (1'h0),
.TXCTRL0 (16'h0),
.TXCTRL1 (16'h0),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA (tx_data_s),
2016-10-19 17:05:59 +00:00
.TXDATAEXTENDRSVD (8'h0),
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
.TXDIFFCTRL (up_tx_diffctrl[3:0]),
2016-10-19 17:05:59 +00:00
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
.TXDLYHOLD (1'h0),
.TXDLYOVRDEN (1'h0),
.TXDLYSRESET (1'h0),
2016-06-14 16:18:56 +00:00
.TXDLYSRESETDONE (),
2016-10-19 17:05:59 +00:00
.TXDLYUPDOWN (1'h0),
.TXELECIDLE (1'h0),
.TXHEADER ({4'b0,tx_header}),
2016-10-19 17:05:59 +00:00
.TXINHIBIT (1'h0),
.TXLATCLK (1'h0),
.TXMAINCURSOR (7'h40),
.TXMARGIN (3'h0),
.TXOUTCLK (tx_out_clk_s),
2016-06-14 16:18:56 +00:00
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
2016-10-19 17:05:59 +00:00
.TXOUTCLKSEL (up_tx_out_clk_sel),
.TXPCSRESET (1'h0),
.TXPD (2'h0),
.TXPDELECIDLEMODE (1'h0),
.TXPHALIGN (1'h0),
2016-06-14 16:18:56 +00:00
.TXPHALIGNDONE (),
2016-10-19 17:05:59 +00:00
.TXPHALIGNEN (1'h0),
.TXPHDLYPD (1'h1),
.TXPHDLYRESET (1'h0),
.TXPHDLYTSTCLK (1'h0),
.TXPHINIT (1'h0),
2016-06-14 16:18:56 +00:00
.TXPHINITDONE (),
2016-10-19 17:05:59 +00:00
.TXPHOVRDEN (1'h0),
.TXPIPPMEN (1'h0),
.TXPIPPMOVRDEN (1'h0),
.TXPIPPMPD (1'h0),
.TXPIPPMSEL (1'h0),
.TXPIPPMSTEPSIZE (5'h0),
.TXPISOPD (1'h0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'h0),
2016-06-14 16:18:56 +00:00
.TXPMARESETDONE (),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor),
2016-10-19 17:05:59 +00:00
.TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (tx_prbssel),
.TXPRECURSOR (up_tx_precursor),
2016-10-19 17:05:59 +00:00
.TXPRECURSORINV (1'h0),
2016-06-14 16:18:56 +00:00
.TXPRGDIVRESETDONE (),
2016-10-19 17:05:59 +00:00
.TXPROGDIVRESET (up_tx_rst),
.TXQPIBIASEN (1'h0),
2016-06-14 16:18:56 +00:00
.TXQPISENN (),
.TXQPISENP (),
2016-10-19 17:05:59 +00:00
.TXQPISTRONGPDOWN (1'h0),
.TXQPIWEAKPUP (1'h0),
.TXRATE (tx_rate_m2),
2016-06-14 16:18:56 +00:00
.TXRATEDONE (),
2016-10-19 17:05:59 +00:00
.TXRATEMODE (1'h0),
.TXRESETDONE (tx_rst_done_s),
2016-10-19 17:05:59 +00:00
.TXSEQUENCE (7'h0),
.TXSWING (1'h0),
.TXSYNCALLIN (1'h0),
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.TXSYNCDONE (),
2016-10-19 17:05:59 +00:00
.TXSYNCIN (1'h0),
.TXSYNCMODE (1'h0),
.TXSYNCOUT (),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_usrclk),
.TXUSRCLK2 (tx_usrclk2));
2016-06-14 16:18:56 +00:00
end
endgenerate
2016-10-05 17:53:02 +00:00
generate
if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin
2016-10-05 17:53:02 +00:00
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
BUFG_GT i_rx_div2_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd1),
.I (rx_out_clk_s),
.O (rx_out_clk_div2));
BUFG_GT i_tx_div2_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd1),
.I (tx_out_clk_s),
.O (tx_out_clk_div2));
2016-10-05 17:53:02 +00:00
end
endgenerate
generate
if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]};
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]};
assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
end
endgenerate
generate
if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin
GTHE4_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
.ADAPT_CFG0 (16'b0001000000000000),
.ADAPT_CFG1 (16'b1100100000000000),
.ADAPT_CFG2 (16'b0000000000000000),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_RXTERMINATION (1'b1),
.A_TXDIFFCTRL (A_TXDIFFCTRL),
.A_TXPROGDIVRESET (1'b0),
.CAPBYPASS_FORCE (1'b0),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CDR_SWAP_MODE_EN (1'b0),
.CFOK_PWRSVE_EN (1'b1),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (CH_HSPMUX),
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0101000011000000),
.CKCAL1_CFG_2 (16'b0000000000001010),
.CKCAL1_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_0 (16'b1100000011000000),
.CKCAL2_CFG_1 (16'b1000000011000000),
.CKCAL2_CFG_2 (16'b0000000000000000),
.CKCAL2_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_4 (16'b0000000000000000),
.CKCAL_RSVD0 (16'b0000000010000000),
.CKCAL_RSVD1 (16'b0000010000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'b0000001010110010),
.CPLL_LOCK_CFG (16'b0000000111101000),
.CPLL_REFCLK_DIV (1),
.CTLE3_OCAP_EXT_CTRL (3'b000),
.CTLE3_OCAP_EXT_EN (1'b0),
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DELAY_ELEC (1'b0),
.DMONITOR_CFG0 (10'b0000000000),
.DMONITOR_CFG1 (8'b00000000),
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'b000000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER0 (16'b0000000000000000),
.ES_QUALIFIER1 (16'b0000000000000000),
.ES_QUALIFIER2 (16'b0000000000000000),
.ES_QUALIFIER3 (16'b0000000000000000),
.ES_QUALIFIER4 (16'b0000000000000000),
.ES_QUALIFIER5 (16'b0000000000000000),
.ES_QUALIFIER6 (16'b0000000000000000),
.ES_QUALIFIER7 (16'b0000000000000000),
.ES_QUALIFIER8 (16'b0000000000000000),
.ES_QUALIFIER9 (16'b0000000000000000),
.ES_QUAL_MASK0 (16'b1111111111111111),
.ES_QUAL_MASK1 (16'b1111111111111111),
.ES_QUAL_MASK2 (16'b1111111111111111),
.ES_QUAL_MASK3 (16'b1111111111111111),
.ES_QUAL_MASK4 (16'b1111111111111111),
.ES_QUAL_MASK5 (16'b1111111111111111),
.ES_QUAL_MASK6 (16'b1111111111111111),
.ES_QUAL_MASK7 (16'b1111111111111111),
.ES_QUAL_MASK8 (16'b1111111111111111),
.ES_QUAL_MASK9 (16'b1111111111111111),
.ES_SDATA_MASK0 (16'b1111111111111111),
.ES_SDATA_MASK1 (16'b1111111111111111),
.ES_SDATA_MASK2 (16'b0000000011111111),
.ES_SDATA_MASK3 (16'b0000000000000000),
.ES_SDATA_MASK4 (16'b0000000000000000),
.ES_SDATA_MASK5 (16'b1111111111111111),
.ES_SDATA_MASK6 (16'b1111111111111111),
.ES_SDATA_MASK7 (16'b1111111111111111),
.ES_SDATA_MASK8 (16'b1111111111111111),
.ES_SDATA_MASK9 (16'b1111111111111111),
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (GEARBOX_MODE),
.ISCAN_CK_PH_SEL2 (1'b0),
.LOCAL_MASTER (1'b1),
.LPBK_BIAS_CTRL (3'b100),
.LPBK_EN_RCAL_B (1'b0),
.LPBK_EXT_RCAL (4'b1000),
.LPBK_IND_CTRL0 (3'b000),
.LPBK_IND_CTRL1 (3'b000),
.LPBK_IND_CTRL2 (3'b000),
.LPBK_RG_CTRL (4'b1110),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
.PCIE3_CLK_COR_EMPTY_THRSH (5'b00000),
.PCIE3_CLK_COR_FULL_THRSH (6'b010000),
.PCIE3_CLK_COR_MAX_LAT (5'b00100),
.PCIE3_CLK_COR_MIN_LAT (5'b00000),
.PCIE3_CLK_COR_THRSH_TIMER (6'b001000),
.PCIE_BUFG_DIV_CTRL (16'b0011010100000000),
.PCIE_PLL_SEL_MODE_GEN12 (2'b10),
.PCIE_PLL_SEL_MODE_GEN3 (2'b10),
.PCIE_PLL_SEL_MODE_GEN4 (2'b10),
.PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101),
.PCIE_RXPMA_CFG (16'b0010100000001010),
.PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100),
.PCIE_TXPMA_CFG (16'b0010100000001010),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.PROCESS_PAR (3'b010),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
.RCLK_SIPO_INV_EN (1'b0),
.RESET_POWERSAVE_DISABLE (1'b0),
.RTX_BUF_CML_CTRL (3'b010),
.RTX_BUF_TERM_CTRL (2'b00),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN (RXBUF_EN),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG0_GEN3 (16'b0000000000000011),
.RXCDR_CFG1 (16'b0000000000000000),
.RXCDR_CFG1_GEN3 (16'b0000000000000000),
.RXCDR_CFG2 (16'b0000001001100101),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN3 (16'b0000001001100101),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.RXCDR_CFG4 (16'b0101110011110110),
.RXCDR_CFG4_GEN3 (16'b0101110011110110),
.RXCDR_CFG5 (16'b1011010001101011),
.RXCDR_CFG5_GEN3 (16'b0001010001101011),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_LOCK_CFG0 (16'b0010001000000001),
.RXCDR_LOCK_CFG1 (16'b1001111111111111),
.RXCDR_LOCK_CFG2 (16'b0111011111000011),
.RXCDR_LOCK_CFG3 (16'b0000000000000001),
.RXCDR_LOCK_CFG4 (16'b0000000000000000),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCFOK_CFG0 (16'b0000000000000000),
.RXCFOK_CFG1 (16'b1000000000010101),
.RXCFOK_CFG2 (16'b0000001010101110),
.RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000100),
.RXDFELPMRESET_TIME (7'b0001111),
.RXDFELPM_KL_CFG0 (16'b0000000000000000),
.RXDFELPM_KL_CFG1 (16'b1010000011100010),
.RXDFELPM_KL_CFG2 (16'b0000000100000000),
.RXDFE_CFG0 (16'b0000101000000000),
.RXDFE_CFG1 (16'b0000000000000000),
.RXDFE_GC_CFG0 (16'b0000000000000000),
.RXDFE_GC_CFG1 (16'b1000000000000000),
.RXDFE_GC_CFG2 (16'b1111111111100000),
.RXDFE_H2_CFG0 (16'b0000000000000000),
.RXDFE_H2_CFG1 (16'b0000000000000010),
.RXDFE_H3_CFG0 (16'b0000000000000000),
.RXDFE_H3_CFG1 (16'b1000000000000010),
.RXDFE_H4_CFG0 (16'b0000000000000000),
.RXDFE_H4_CFG1 (16'b1000000000000010),
.RXDFE_H5_CFG0 (16'b0000000000000000),
.RXDFE_H5_CFG1 (16'b1000000000000010),
.RXDFE_H6_CFG0 (16'b0000000000000000),
.RXDFE_H6_CFG1 (16'b1000000000000010),
.RXDFE_H7_CFG0 (16'b0000000000000000),
.RXDFE_H7_CFG1 (16'b1000000000000010),
.RXDFE_H8_CFG0 (16'b0000000000000000),
.RXDFE_H8_CFG1 (16'b1000000000000010),
.RXDFE_H9_CFG0 (16'b0000000000000000),
.RXDFE_H9_CFG1 (16'b1000000000000010),
.RXDFE_HA_CFG0 (16'b0000000000000000),
.RXDFE_HA_CFG1 (16'b1000000000000010),
.RXDFE_HB_CFG0 (16'b0000000000000000),
.RXDFE_HB_CFG1 (16'b1000000000000010),
.RXDFE_HC_CFG0 (16'b0000000000000000),
.RXDFE_HC_CFG1 (16'b1000000000000010),
.RXDFE_HD_CFG0 (16'b0000000000000000),
.RXDFE_HD_CFG1 (16'b1000000000000010),
.RXDFE_HE_CFG0 (16'b0000000000000000),
.RXDFE_HE_CFG1 (16'b1000000000000010),
.RXDFE_HF_CFG0 (16'b0000000000000000),
.RXDFE_HF_CFG1 (16'b1000000000000010),
.RXDFE_KH_CFG0 (16'b0000000000000000),
.RXDFE_KH_CFG1 (16'b1000000000000000),
.RXDFE_KH_CFG2 (16'b0010011000010011),
.RXDFE_KH_CFG3 (16'b0100000100011100),
.RXDFE_OS_CFG0 (16'b0000000000000000),
.RXDFE_OS_CFG1 (16'b1000000000000010),
.RXDFE_PWR_SAVING (1'b0),
.RXDFE_UT_CFG0 (16'b0000000000000000),
.RXDFE_UT_CFG1 (16'b0000000000000011),
.RXDFE_UT_CFG2 (16'b0000000000000000),
.RXDFE_VP_CFG0 (16'b0000000000000000),
.RXDFE_VP_CFG1 (16'b1000000000110011),
.RXDLY_CFG (16'b0000000000010000),
.RXDLY_LCFG (16'b0000000000110000),
.RXELECIDLE_CFG ("SIGCFG_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
.RXGEARBOX_EN (RXGEARBOX_EN),
.RXISCANRESET_TIME (5'b00001),
.RXLPM_CFG (16'b0000000000000000),
.RXLPM_GC_CFG (16'b1000000000000000),
.RXLPM_KH_CFG0 (16'b0000000000000000),
.RXLPM_KH_CFG1 (16'b0000000000000010),
.RXLPM_OS_CFG0 (16'b0000000000000000),
.RXLPM_OS_CFG1 (16'b1000000000000010),
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
.RXPHBEACON_CFG (16'b0000000000000000),
.RXPHDLY_CFG (16'b0010000001110000),
.RXPHSAMP_CFG (16'b0010000100000000),
.RXPHSLIP_CFG (16'b1001100100110011),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_AUTO_BW_SEL_BYPASS (1'b0),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_LPM (1'b0),
.RXPI_SEL_LC (2'b00),
.RXPI_STARTCODE (2'b00),
.RXPI_VREFSEL (1'b0),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXREFCLKDIV2_SEL (1'b0),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
.RX_BIAS_CFG0 (16'b0001010101010100),
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (3),
.RX_CM_TRIM (10),
.RX_CTLE3_LPF (8'b11111111),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DEGEN_CTRL (3'b011),
.RX_DFELPM_CFG0 (6),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG0 (2'b10),
.RX_DFE_AGC_CFG1 (4),
.RX_DFE_KL_LPM_KH_CFG0 (1),
.RX_DFE_KL_LPM_KH_CFG1 (4),
.RX_DFE_KL_LPM_KL_CFG0 (2'b01),
.RX_DFE_KL_LPM_KL_CFG1 (4),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIV2_MODE_B (1'b0),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_CTLE_RCAL_B (1'b0),
.RX_EN_HI_LR (1'b1),
.RX_EXT_RL_CTRL (9'b000000000),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b00),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
.RX_INT_DATAWIDTH (1),
.RX_PMA_POWER_SAVE (1'b0),
.RX_PMA_RSV0 (16'b0000000000000000),
.RX_PROGDIV_CFG (0.0),
.RX_PROGDIV_RATE (16'b0000000000000001),
.RX_RESLOAD_CTRL (4'b0000),
.RX_RESLOAD_OVRD (1'b0),
.RX_SAMPLE_PERIOD (3'b111),
.RX_SIG_VALID_DLY (11),
.RX_SUM_DFETAPREP_EN (1'b0),
.RX_SUM_IREF_TUNE (4'b0100),
.RX_SUM_RESLOAD_CTRL (4'b0011),
.RX_SUM_VCMTUNE (4'b0110),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b100),
.RX_TUNE_AFE_OS (2'b00),
.RX_VREG_CTRL (3'b101),
.RX_VREG_PDB (1'b1),
.RX_WIDEMODE_CDR (2'b01),
.RX_WIDEMODE_CDR_GEN3 (2'b00),
.RX_WIDEMODE_CDR_GEN4 (2'b01),
.RX_XCLK_SEL ("RXDES"),
.RX_XMODE_SEL (1'b0),
.SAMPLE_CLK_PHASE (1'b0),
.SAS_12G_MODE (1'b0),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_MODE ("FAST"),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
.SRSTMODE (1'b0),
.TAPDLY_SET_TX (2'b00),
.TEMPERATURE_PAR (4'b0010),
.TERM_RCAL_CFG (15'b100001000010001),
.TERM_RCAL_OVRD (3'b000),
.TRANS_TIME_RATE (8'b00001110),
.TST_RSV0 (8'b00000000),
.TST_RSV1 (8'b00000000),
.TXBUF_EN (TXBUF_EN),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'b1000000000010000),
.TXDLY_LCFG (16'b0000000000110000),
.TXDRVBIAS_N (4'b1010),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN (TXGEARBOX_EN),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
.TXPHDLY_CFG0 (16'b0110000001110000),
.TXPHDLY_CFG1 (16'b0000000000001111),
.TXPH_CFG (16'b0000001100100011),
.TXPH_CFG2 (16'b0000000000000000),
.TXPH_MONITOR_SEL (5'b00000),
.TXPI_CFG (TXPI_CFG),
.TXPI_CFG0 (2'b00),
.TXPI_CFG1 (2'b00),
.TXPI_CFG2 (2'b00),
.TXPI_CFG3 (1'b0),
.TXPI_CFG4 (1'b0),
.TXPI_CFG5 (3'b000),
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_LPM (1'b0),
.TXPI_PPM (1'b0),
.TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.TXPI_PPM_CFG (8'b00000000),
.TXPI_SYNFREQ_PPM (3'b001),
.TXPI_VREFSEL (1'b0),
.TXPMARESET_TIME (5'b00011),
.TXREFCLKDIV2_SEL (1'b0),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DEEMPH2 (6'b000000),
.TX_DEEMPH3 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_DRVMUX_CTRL (2),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_FIFO_BYP_EN (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
.TX_INT_DATAWIDTH (1),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1011111),
.TX_MARGIN_FULL_1 (7'b1011110),
.TX_MARGIN_FULL_2 (7'b1011100),
.TX_MARGIN_FULL_3 (7'b1011010),
.TX_MARGIN_FULL_4 (7'b1011000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000101),
.TX_MARGIN_LOW_2 (7'b1000011),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
.TX_PHICAL_CFG0 (16'b0000000000000000),
.TX_PHICAL_CFG1 (16'b0111111000000000),
.TX_PHICAL_CFG2 (16'b0000001000000001),
.TX_PI_BIASSET (TX_PI_BIASSET),
.TX_PI_IBIAS_MID (2'b00),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
.TX_PMA_RSV0 (16'b0000000000001000),
.TX_PREDRV_CTRL (2),
.TX_PROGCLK_SEL ("PREPI"),
.TX_PROGDIV_CFG (0.0),
.TX_PROGDIV_RATE (16'b0000000000000001),
.TX_QPI_STATUS_EN (1'b0),
.TX_RXDETECT_CFG (14'b00000000110010),
.TX_RXDETECT_REF (4),
.TX_SAMPLE_PERIOD (3'b111),
.TX_SARC_LPBK_ENB (1'b0),
.TX_SW_MEAS (2'b00),
.TX_VREG_CTRL (3'b000),
.TX_VREG_PDB (1'b0),
.TX_VREG_VREFSEL (2'b00),
.TX_XCLK_SEL ("TXOUT"),
.USB_BOTH_BURST_IDLE (1'b0),
.USB_BURSTMAX_U3WAKE (7'b1111111),
.USB_BURSTMIN_U3WAKE (7'b1100011),
.USB_CLK_COR_EQ_EN (1'b0),
.USB_EXT_CNTL (1'b1),
.USB_IDLEMAX_POLLING (10'b1010111011),
.USB_IDLEMIN_POLLING (10'b0100101011),
.USB_LFPSPING_BURST (9'b000000101),
.USB_LFPSPOLLING_BURST (9'b000110001),
.USB_LFPSPOLLING_IDLE_MS (9'b000000100),
.USB_LFPSU1EXIT_BURST (9'b000011101),
.USB_LFPSU2LPEXIT_BURST_MS (9'b001100011),
.USB_LFPSU3WAKE_BURST_MS (9'b111110011),
.USB_LFPS_TPERIOD (4'b0011),
.USB_LFPS_TPERIOD_ACCURATE (1'b1),
.USB_MODE (1'b0),
.USB_PCIE_ERR_REP_DIS (1'b0),
.USB_PING_SATA_MAX_INIT (21),
.USB_PING_SATA_MIN_INIT (12),
.USB_POLL_SATA_MAX_BURST (8),
.USB_POLL_SATA_MIN_BURST (4),
.USB_RAW_ELEC (1'b0),
.USB_RXIDLE_P0_CTRL (1'b1),
.USB_TXIDLE_TUNE_ENABLE (1'b1),
.USB_U1_SATA_MAX_WAKE (7),
.USB_U1_SATA_MIN_WAKE (4),
.USB_U2_SAS_MAX_COM (64),
.USB_U2_SAS_MIN_COM (36),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.Y_ALL_MODE (1'b0))
i_gthe4_channel (
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
.CDRSTEPDIR (1'd0),
.CDRSTEPSQ (1'd0),
.CDRSTEPSX (1'd0),
.CFGRESET (1'd0),
.CLKRSVD0 (1'd0),
.CLKRSVD1 (1'd0),
.CPLLFBCLKLOST (),
.CPLLFREQLOCK (1'd0),
.CPLLLOCK (cpll_locked_s),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'd1),
.CPLLPD (up_cpll_rst),
.CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (1'b0),
.DMONFIFORESET (1'd0),
.DMONITORCLK (1'd0),
.DMONITOROUT (),
.DMONITOROUTCLK (),
.DRPADDR (up_addr_int[9:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPRST (1'd0),
.DRPWE (up_wr_int),
.EYESCANDATAERROR (),
.EYESCANRESET (up_es_reset),
.EYESCANTRIGGER (1'd0),
.FREQOS (1'd0),
.GTGREFCLK (1'd0),
.GTHRXN (rx_n),
.GTHRXP (rx_p),
.GTHTXN (tx_n),
.GTHTXP (tx_p),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTPOWERGOOD (),
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'd0),
.GTREFCLKMONITOR (),
.GTRSVD (15'd0),
.GTRXRESET (up_rx_rst),
.GTRXRESETSEL (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.GTTXRESET (up_tx_rst),
.GTTXRESETSEL (1'd0),
.INCPCTRL (1'd0),
.LOOPBACK (3'd0),
.PCIEEQRXEQADAPTDONE (1'd0),
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
.PCIERSTIDLE (1'd0),
.PCIERSTTXSYNCSTART (1'd0),
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
.PCIEUSERRATEDONE (1'd0),
.PCIEUSERRATESTART (),
.PCSRSVDIN (16'd0),
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
.POWERPRESENT (),
.QPLL0CLK (qpll2ch_clk),
.QPLL0FREQLOCK (1'd0),
.QPLL0REFCLK (qpll2ch_ref_clk),
.QPLL1CLK (qpll1_clk),
.QPLL1FREQLOCK (1'd0),
.QPLL1REFCLK (qpll1_ref_clk),
.RESETEXCEPTION (),
.RESETOVRD (1'd0),
.RX8B10BEN (RX8B10BEN),
.RXAFECFOKEN (1'b1),
.RXBUFRESET (1'd0),
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCDRFREQRESET (1'd0),
.RXCDRHOLD (1'd0),
.RXCDRLOCK (),
.RXCDROVRDEN (1'd0),
.RXCDRPHDONE (),
.RXCDRRESET (1'd0),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCHBONDEN (1'd0),
.RXCHBONDI (5'd0),
.RXCHBONDLEVEL (3'd0),
.RXCHBONDMASTER (1'd0),
.RXCHBONDO (),
.RXCHBONDSLAVE (1'd0),
.RXCKCALDONE (),
.RXCKCALRESET (1'd0),
.RXCKCALSTART (7'd0),
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
.RXCOMMADETEN (1'd1),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
.RXCTRL2 (),
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA (rx_data_s),
.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
.RXDFEAGCCTRL (2'b01),
.RXDFEAGCHOLD (1'd0),
.RXDFEAGCOVRDEN (1'd0),
.RXDFECFOKFCNUM (4'b1101),
.RXDFECFOKFEN (1'd0),
.RXDFECFOKFPULSE (1'd0),
.RXDFECFOKHOLD (1'd0),
.RXDFECFOKOVREN (1'd0),
.RXDFEKHHOLD (1'd0),
.RXDFEKHOVRDEN (1'd0),
.RXDFELFHOLD (1'd0),
.RXDFELFOVRDEN (1'd0),
.RXDFELPMRESET (1'd0),
.RXDFETAP10HOLD (1'd0),
.RXDFETAP10OVRDEN (1'd0),
.RXDFETAP11HOLD (1'd0),
.RXDFETAP11OVRDEN (1'd0),
.RXDFETAP12HOLD (1'd0),
.RXDFETAP12OVRDEN (1'd0),
.RXDFETAP13HOLD (1'd0),
.RXDFETAP13OVRDEN (1'd0),
.RXDFETAP14HOLD (1'd0),
.RXDFETAP14OVRDEN (1'd0),
.RXDFETAP15HOLD (1'd0),
.RXDFETAP15OVRDEN (1'd0),
.RXDFETAP2HOLD (1'd0),
.RXDFETAP2OVRDEN (1'd0),
.RXDFETAP3HOLD (1'd0),
.RXDFETAP3OVRDEN (1'd0),
.RXDFETAP4HOLD (1'd0),
.RXDFETAP4OVRDEN (1'd0),
.RXDFETAP5HOLD (1'd0),
.RXDFETAP5OVRDEN (1'd0),
.RXDFETAP6HOLD (1'd0),
.RXDFETAP6OVRDEN (1'd0),
.RXDFETAP7HOLD (1'd0),
.RXDFETAP7OVRDEN (1'd0),
.RXDFETAP8HOLD (1'd0),
.RXDFETAP8OVRDEN (1'd0),
.RXDFETAP9HOLD (1'd0),
.RXDFETAP9OVRDEN (1'd0),
.RXDFEUTHOLD (1'd0),
.RXDFEUTOVRDEN (1'd0),
.RXDFEVPHOLD (1'd0),
.RXDFEVPOVRDEN (1'd0),
.RXDFEXYDEN (1'd1),
.RXDLYBYPASS (1'd1),
.RXDLYEN (1'd0),
.RXDLYOVRDEN (1'd0),
.RXDLYSRESET (1'd0),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXELECIDLEMODE (2'b11),
.RXEQTRAINING (1'd0),
.RXGEARBOXSLIP (rx_bitslip_s),
.RXHEADER (rx_header_s),
.RXHEADERVALID (),
.RXLATCLK (1'd0),
.RXLFPSTRESETDET (),
.RXLFPSU2LPEXITDET (),
.RXLFPSU3WAKEDET (),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMGCHOLD (1'd0),
.RXLPMGCOVRDEN (1'd0),
.RXLPMHFHOLD (1'd0),
.RXLPMHFOVRDEN (1'd0),
.RXLPMLFHOLD (1'd0),
.RXLPMLFKLOVRDEN (1'd0),
.RXLPMOSHOLD (1'd0),
.RXLPMOSOVRDEN (1'd0),
.RXMCOMMAALIGNEN (rx_calign),
.RXMONITOROUT (),
.RXMONITORSEL (2'd0),
.RXOOBRESET (1'd0),
.RXOSCALRESET (1'd0),
.RXOSHOLD (1'd0),
.RXOSINTDONE (),
.RXOSINTSTARTED (),
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
.RXOSOVRDEN (1'd0),
.RXOUTCLK (rx_out_clk_s),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (up_rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'd0),
.RXPD (2'd0),
.RXPHALIGN (1'd0),
.RXPHALIGNDONE (),
.RXPHALIGNEN (1'd0),
.RXPHALIGNERR (),
.RXPHDLYPD (1'd1),
.RXPHDLYRESET (1'd0),
.RXPHOVRDEN (1'd0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'd0),
.RXPMARESETDONE (),
.RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSERR (rx_prbserr),
.RXPRBSLOCKED (rx_prbslocked),
.RXPRBSSEL (rx_prbssel),
.RXPRGDIVRESETDONE (),
2021-05-18 10:26:43 +00:00
.RXPROGDIVRESET (up_rx_rst),
.RXQPIEN (1'd0),
.RXQPISENN (),
.RXQPISENP (),
.RXRATE (rx_rate_m2),
.RXRATEDONE (),
.RXRATEMODE (1'd0),
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done_s),
.RXSLIDE (1'd0),
.RXSLIDERDY (),
.RXSLIPDONE (),
.RXSLIPOUTCLK (1'd0),
.RXSLIPOUTCLKRDY (),
.RXSLIPPMA (1'd0),
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
.RXSYNCALLIN (1'd0),
.RXSYNCDONE (),
.RXSYNCIN (1'd0),
.RXSYNCMODE (1'd0),
.RXSYNCOUT (),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXTERMINATION (1'd0),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_usrclk),
.RXUSRCLK2 (rx_usrclk2),
.RXVALID (),
.SIGVALIDCLK (1'd0),
.TSTIN (20'd0),
.TX8B10BBYPASS (8'd0),
.TX8B10BEN (RX8B10BEN),
.TXBUFSTATUS (),
.TXCOMFINISH (),
.TXCOMINIT (1'd0),
.TXCOMSAS (1'd0),
.TXCOMWAKE (1'd0),
.TXCTRL0 (16'd0),
.TXCTRL1 (16'd0),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA (tx_data_s),
.TXDATAEXTENDRSVD (8'd0),
.TXDCCDONE (),
.TXDCCFORCESTART (1'd0),
.TXDCCRESET (1'd0),
.TXDEEMPH (2'd0),
.TXDETECTRX (1'd0),
.TXDIFFCTRL ({up_tx_diffctrl, 1'b0}),
.TXDLYBYPASS (1'd1),
.TXDLYEN (1'd0),
.TXDLYHOLD (1'd0),
.TXDLYOVRDEN (1'd0),
.TXDLYSRESET (1'd0),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (1'd0),
.TXELECIDLE (1'd0),
.TXHEADER ({4'b0,tx_header}),
.TXINHIBIT (1'd0),
.TXLATCLK (1'd0),
.TXLFPSTRESET (1'd0),
.TXLFPSU2LPEXIT (1'd0),
.TXLFPSU3WAKE (1'd0),
.TXMAINCURSOR (7'b1000000),
.TXMARGIN (3'd0),
.TXMUXDCDEXHOLD (1'd0),
.TXMUXDCDORWREN (1'd0),
.TXONESZEROS (1'd0),
.TXOUTCLK (tx_out_clk_s),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXOUTCLKSEL (up_tx_out_clk_sel),
.TXPCSRESET (1'd0),
.TXPD (2'd0),
.TXPDELECIDLEMODE (1'd0),
.TXPHALIGN (1'd0),
.TXPHALIGNDONE (),
.TXPHALIGNEN (1'd0),
.TXPHDLYPD (1'd1),
.TXPHDLYRESET (1'd0),
.TXPHDLYTSTCLK (1'd0),
.TXPHINIT (1'd0),
.TXPHINITDONE (),
.TXPHOVRDEN (1'd0),
.TXPIPPMEN (1'd0),
.TXPIPPMOVRDEN (1'd0),
.TXPIPPMPD (1'd0),
.TXPIPPMSEL (1'd0),
.TXPIPPMSTEPSIZE (5'd0),
.TXPISOPD (1'd0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'd0),
.TXPMARESETDONE (),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor),
.TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (tx_prbssel),
.TXPRECURSOR (up_tx_precursor),
.TXPRGDIVRESETDONE (),
.TXPROGDIVRESET (up_tx_rst),
.TXQPIBIASEN (1'd0),
.TXQPISENN (),
.TXQPISENP (),
.TXQPIWEAKPUP (1'd0),
.TXRATE (tx_rate_m2),
.TXRATEDONE (),
.TXRATEMODE (1'd0),
.TXRESETDONE (tx_rst_done_s),
.TXSEQUENCE (7'd0),
.TXSWING (1'd0),
.TXSYNCALLIN (1'd0),
.TXSYNCDONE (),
.TXSYNCIN (1'd0),
.TXSYNCMODE (1'd0),
.TXSYNCOUT (),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_usrclk),
.TXUSRCLK2 (tx_usrclk2));
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]};
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]};
assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
GTYE4_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
.ADAPT_CFG0 (16'b0000000000000000),
.ADAPT_CFG1 (16'b1111101100011100),
.ADAPT_CFG2 (16'b0000000000000000),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_RXTERMINATION (1'b1),
.A_TXDIFFCTRL (5'b01100),
.A_TXPROGDIVRESET (1'b0),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CDR_SWAP_MODE_EN (1'b0),
.CFOK_PWRSVE_EN (1'b1),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (CH_HSPMUX),
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0001000011000000),
.CKCAL1_CFG_2 (16'b0010000000001000),
.CKCAL1_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_0 (16'b1100000011000000),
.CKCAL2_CFG_1 (16'b1000000011000000),
.CKCAL2_CFG_2 (16'b0001000000000000),
.CKCAL2_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_4 (16'b0000000000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'b0000001010110010),
.CPLL_LOCK_CFG (16'b0000000111101000),
.CPLL_REFCLK_DIV (1),
.CTLE3_OCAP_EXT_CTRL (3'b000),
.CTLE3_OCAP_EXT_EN (1'b0),
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DELAY_ELEC (1'b0),
.DMONITOR_CFG0 (10'b0000000000),
.DMONITOR_CFG1 (8'b00000000),
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
2019-12-18 14:36:43 +00:00
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'b000000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER0 (16'b0000000000000000),
.ES_QUALIFIER1 (16'b0000000000000000),
.ES_QUALIFIER2 (16'b0000000000000000),
.ES_QUALIFIER3 (16'b0000000000000000),
.ES_QUALIFIER4 (16'b0000000000000000),
.ES_QUALIFIER5 (16'b0000000000000000),
.ES_QUALIFIER6 (16'b0000000000000000),
.ES_QUALIFIER7 (16'b0000000000000000),
.ES_QUALIFIER8 (16'b0000000000000000),
.ES_QUALIFIER9 (16'b0000000000000000),
2019-12-18 14:36:43 +00:00
.ES_QUAL_MASK0 (16'b1111111111111111),
.ES_QUAL_MASK1 (16'b1111111111111111),
.ES_QUAL_MASK2 (16'b1111111111111111),
.ES_QUAL_MASK3 (16'b1111111111111111),
.ES_QUAL_MASK4 (16'b1111111111111111),
.ES_QUAL_MASK5 (16'b1111111111111111),
.ES_QUAL_MASK6 (16'b1111111111111111),
.ES_QUAL_MASK7 (16'b1111111111111111),
.ES_QUAL_MASK8 (16'b1111111111111111),
.ES_QUAL_MASK9 (16'b1111111111111111),
.ES_SDATA_MASK0 (16'b1111111111111111),
.ES_SDATA_MASK1 (16'b1111111111111111),
.ES_SDATA_MASK2 (16'b0000000011111111),
.ES_SDATA_MASK3 (16'b0000000000000000),
.ES_SDATA_MASK4 (16'b0000000000000000),
2019-12-18 14:36:43 +00:00
.ES_SDATA_MASK5 (16'b1111111111111111),
.ES_SDATA_MASK6 (16'b1111111111111111),
.ES_SDATA_MASK7 (16'b1111111111111111),
.ES_SDATA_MASK8 (16'b1111111111111111),
.ES_SDATA_MASK9 (16'b1111111111111111),
.EYESCAN_VP_RANGE (0),
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (GEARBOX_MODE),
.ISCAN_CK_PH_SEL2 (1'b0),
.LOCAL_MASTER (1'b1),
.LPBK_BIAS_CTRL (4),
.LPBK_EN_RCAL_B (1'b0),
.LPBK_EXT_RCAL (4'b1000),
.LPBK_IND_CTRL0 (5),
.LPBK_IND_CTRL1 (5),
.LPBK_IND_CTRL2 (5),
.LPBK_RG_CTRL (2),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
.PCIE3_CLK_COR_EMPTY_THRSH (5'b00000),
.PCIE3_CLK_COR_FULL_THRSH (6'b010000),
.PCIE3_CLK_COR_MAX_LAT (5'b00100),
.PCIE3_CLK_COR_MIN_LAT (5'b00000),
.PCIE3_CLK_COR_THRSH_TIMER (6'b001000),
.PCIE_64B_DYN_CLKSW_DIS ("FALSE"),
.PCIE_BUFG_DIV_CTRL (16'b0011010100000000),
.PCIE_GEN4_64BIT_INT_EN ("FALSE"),
.PCIE_PLL_SEL_MODE_GEN12 (2'b10),
.PCIE_PLL_SEL_MODE_GEN3 (2'b10),
.PCIE_PLL_SEL_MODE_GEN4 (2'b10),
.PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101),
.PCIE_RXPMA_CFG (16'b0010100000001010),
.PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100),
.PCIE_TXPMA_CFG (16'b0010100000001010),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
.RCLK_SIPO_INV_EN (1'b0),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL),
.RTX_BUF_TERM_CTRL (2'b00),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN (RXBUF_EN),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXCDR_CFG0 (16'b0000000000000011),
.RXCDR_CFG0_GEN3 (16'b0000000000000011),
.RXCDR_CFG1 (16'b0000000000000000),
.RXCDR_CFG1_GEN3 (16'b0000000000000000),
.RXCDR_CFG2 (RXCDR_CFG2),
.RXCDR_CFG2_GEN2 (10'b1001101001),
.RXCDR_CFG2_GEN3 (16'b0000001001101001),
.RXCDR_CFG2_GEN4 (16'b0000000101100100),
.RXCDR_CFG3 (16'b0000000000010010),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.RXCDR_CFG4 (16'b0101110011110110),
.RXCDR_CFG4_GEN3 (16'b0101110011110110),
.RXCDR_CFG5 (16'b1011010001101011),
.RXCDR_CFG5_GEN3 (16'b0001010001101011),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_LOCK_CFG0 (16'b0010001000000001),
.RXCDR_LOCK_CFG1 (16'b1001111111111111),
.RXCDR_LOCK_CFG2 (15'b000000000000000 ),
.RXCDR_LOCK_CFG3 (16'b0000000000000000),
.RXCDR_LOCK_CFG4 (16'b0000000000000000),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCFOK_CFG0 (16'b0000000000000000),
.RXCFOK_CFG1 (16'b1000000000010101),
.RXCFOK_CFG2 (16'b0000001010101110),
.RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000000),
.RXDFELPMRESET_TIME (7'b0001111),
.RXDFELPM_KL_CFG0 (15'b000000000000000),
.RXDFELPM_KL_CFG1 (16'b1010000010000010),
.RXDFELPM_KL_CFG2 (16'b0000000100000000),
.RXDFE_CFG0 (16'b0000101000000000),
.RXDFE_CFG1 (16'b0000000000000000),
.RXDFE_GC_CFG0 (16'b0000000000000000),
.RXDFE_GC_CFG1 (16'b1000000000000000),
.RXDFE_GC_CFG2 (16'b1111111111100000),
.RXDFE_H2_CFG0 (16'b0000000000000000),
.RXDFE_H2_CFG1 (16'b0000000000000010),
.RXDFE_H3_CFG0 (16'b0000000000000000),
.RXDFE_H3_CFG1 (16'b1000000000000010),
.RXDFE_H4_CFG0 (16'b0000000000000000),
.RXDFE_H4_CFG1 (16'b1000000000000010),
.RXDFE_H5_CFG0 (16'b0000000000000000),
.RXDFE_H5_CFG1 (16'b1000000000000010),
.RXDFE_H6_CFG0 (16'b0000000000000000),
.RXDFE_H6_CFG1 (16'b1000000000000010),
.RXDFE_H7_CFG0 (16'b0000000000000000),
.RXDFE_H7_CFG1 (16'b1000000000000010),
.RXDFE_H8_CFG0 (16'b0000000000000000),
.RXDFE_H8_CFG1 (16'b1000000000000010),
.RXDFE_H9_CFG0 (16'b0000000000000000),
.RXDFE_H9_CFG1 (16'b1000000000000010),
.RXDFE_HA_CFG0 (16'b0000000000000000),
.RXDFE_HA_CFG1 (16'b1000000000000010),
.RXDFE_HB_CFG0 (16'b0000000000000000),
.RXDFE_HB_CFG1 (16'b1000000000000010),
.RXDFE_HC_CFG0 (16'b0000000000000000),
.RXDFE_HC_CFG1 (16'b1000000000000010),
.RXDFE_HD_CFG0 (16'b0000000000000000),
.RXDFE_HD_CFG1 (16'b1000000000000010),
.RXDFE_HE_CFG0 (16'b0000000000000000),
.RXDFE_HE_CFG1 (16'b1000000000000010),
.RXDFE_HF_CFG0 (16'b0000000000000000),
.RXDFE_HF_CFG1 (16'b1000000000000010),
.RXDFE_KH_CFG0 (16'b1000000000000000),
.RXDFE_KH_CFG1 (16'b1111111000000000),
.RXDFE_KH_CFG2 (RXDFE_KH_CFG2),
.RXDFE_KH_CFG3 (RXDFE_KH_CFG3),
.RXDFE_OS_CFG0 (16'b0010000000000000),
.RXDFE_OS_CFG1 (16'b1000000000000000),
.RXDFE_UT_CFG0 (16'b0000000000000000),
.RXDFE_UT_CFG1 (16'b0000000000000011),
.RXDFE_UT_CFG2 (16'b0000000000000000),
.RXDFE_VP_CFG0 (16'b0000000000000000),
.RXDFE_VP_CFG1 (16'b0000000000110011),
.RXDLY_CFG (16'b0000000000010000),
.RXDLY_LCFG (16'b0000000000110000),
.RXELECIDLE_CFG ("SIGCFG_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
.RXGEARBOX_EN (RXGEARBOX_EN),
.RXISCANRESET_TIME (5'b00001),
.RXLPM_CFG (16'b0000000000000000),
.RXLPM_GC_CFG (16'b1111100000000000),
.RXLPM_KH_CFG0 (16'b0000000000000000),
.RXLPM_KH_CFG1 (16'b1010000000000010),
.RXLPM_OS_CFG0 (16'b0000000000000000),
.RXLPM_OS_CFG1 (16'b1000000000000010),
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
.RXPHBEACON_CFG (16'b0000000000000000),
.RXPHDLY_CFG (16'b0010000001110000),
.RXPHSAMP_CFG (16'b0010000100000000),
.RXPHSLIP_CFG (16'b1001100100110011),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXREFCLKDIV2_SEL (1'b0),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
.RX_BIAS_CFG0 (16'b0001001010110000),
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (3),
.RX_CM_TRIM (10),
.RX_CTLE_PWR_SAVING (1'b0),
.RX_CTLE_RES_CTRL (4'b0000),
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DEGEN_CTRL (3'b100),
.RX_DFELPM_CFG0 (10),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG1 (2),
.RX_DFE_KL_LPM_KH_CFG0 (3),
.RX_DFE_KL_LPM_KH_CFG1 (2),
.RX_DFE_KL_LPM_KL_CFG0 (2'b11),
.RX_DFE_KL_LPM_KL_CFG1 (2),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_CTLE_RCAL_B (1'b0),
.RX_EN_SUM_RCAL_B (0),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b00),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
.RX_I2V_FILTER_EN (1'b1),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_PMA_POWER_SAVE (1'b0),
.RX_PMA_RSV0 (16'b0000000000101111),
.RX_PROGDIV_CFG (0.0),
.RX_PROGDIV_RATE (16'b0000000000000001),
.RX_RESLOAD_CTRL (4'b0000),
.RX_RESLOAD_OVRD (1'b0),
.RX_SAMPLE_PERIOD (3'b111),
.RX_SIG_VALID_DLY (11),
.RX_SUM_DEGEN_AVTT_OVERITE (0),
.RX_SUM_DFETAPREP_EN (1'b0),
.RX_SUM_IREF_TUNE (4'b0000),
.RX_SUM_PWR_SAVING (0),
.RX_SUM_RES_CTRL (4'b0000),
.RX_SUM_VCMTUNE (4'b0011),
.RX_SUM_VCM_BIAS_TUNE_EN (1'b1),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b100),
.RX_TUNE_AFE_OS (2'b10),
.RX_VREG_CTRL (3'b010),
.RX_VREG_PDB (1'b1),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR),
.RX_WIDEMODE_CDR_GEN3 (2'b00),
.RX_WIDEMODE_CDR_GEN4 (2'b01),
.RX_XCLK_SEL ("RXDES"),
.RX_XMODE_SEL (RX_XMODE_SEL),
.SAMPLE_CLK_PHASE (1'b0),
.SAS_12G_MODE (1'b0),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_MODE ("FAST"),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.SRSTMODE (1'b0),
.TAPDLY_SET_TX (2'b00),
.TERM_RCAL_CFG (15'b100001000000010),
.TERM_RCAL_OVRD (3'b001),
.TRANS_TIME_RATE (8'b00001110),
.TST_RSV0 (8'b00000000),
.TST_RSV1 (8'b00000000),
.TXBUF_EN (TXBUF_EN),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'b1000000000010000),
.TXDLY_LCFG (16'b0000000000110000),
.TXDRV_FREQBAND (TXDRV_FREQBAND),
.TXFE_CFG0 (TXFE_CFG0),
.TXFE_CFG1 (TXFE_CFG1),
.TXFE_CFG2 (TXFE_CFG2),
.TXFE_CFG3 (TXFE_CFG3),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN (TXGEARBOX_EN),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
.TXPHDLY_CFG0 (16'b0110000001110000),
.TXPHDLY_CFG1 (16'h000F),
.TXPH_CFG (16'h0323),
.TXPH_CFG2 (16'b0000000000000000),
.TXPH_MONITOR_SEL (5'b00000),
.TXPI_CFG0 (TXPI_CFG0),
.TXPI_CFG1 (TXPI_CFG1),
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_PPM (1'b0),
.TXPI_PPM_CFG (8'b00000000),
.TXPI_SYNFREQ_PPM (3'b001),
.TXPMARESET_TIME (5'b00011),
.TXREFCLKDIV2_SEL (1'b0),
.TXSWBST_BST (1),
.TXSWBST_EN (TXSWBST_EN),
.TXSWBST_MAG (4),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DEEMPH2 (6'b000000),
.TX_DEEMPH3 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_FIFO_BYP_EN (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1011000),
.TX_MARGIN_FULL_1 (7'b1010111),
.TX_MARGIN_FULL_2 (7'b1010101),
.TX_MARGIN_FULL_3 (7'b1010011),
.TX_MARGIN_FULL_4 (7'b1010001),
.TX_MARGIN_LOW_0 (7'b1001100),
.TX_MARGIN_LOW_1 (7'b1001011),
.TX_MARGIN_LOW_2 (7'b1001000),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
.TX_PHICAL_CFG0 (16'b0000000000100000),
.TX_PHICAL_CFG1 (16'b0000000001000000),
.TX_PI_BIASSET (TX_PI_BIASSET),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
.TX_PMA_RSV0 (16'b0000000000000000),
.TX_PMA_RSV1 (16'b0000000000000000),
.TX_PROGCLK_SEL ("PREPI"),
.TX_PROGDIV_CFG (0.0),
.TX_PROGDIV_RATE (16'b0000000000000001),
.TX_RXDETECT_CFG (14'h032),
.TX_RXDETECT_REF (5),
.TX_SAMPLE_PERIOD (3'b111),
.TX_SW_MEAS (2'b00),
.TX_VREG_CTRL (3'b011),
.TX_VREG_PDB (1'b1),
.TX_VREG_VREFSEL (2'b10),
.TX_XCLK_SEL ("TXOUT"),
.USB_BOTH_BURST_IDLE (1'b0),
.USB_BURSTMAX_U3WAKE (7'b1111111),
.USB_BURSTMIN_U3WAKE (7'b1100011),
.USB_CLK_COR_EQ_EN (1'b0),
.USB_EXT_CNTL (1'b1),
.USB_IDLEMAX_POLLING (10'b1010111011),
.USB_IDLEMIN_POLLING (10'b0100101011),
.USB_LFPSPING_BURST (9'b000000101),
.USB_LFPSPOLLING_BURST (9'b000110001),
.USB_LFPSPOLLING_IDLE_MS (9'b000000100),
.USB_LFPSU1EXIT_BURST (9'b000011101),
.USB_LFPSU2LPEXIT_BURST_MS (9'b001100011),
.USB_LFPSU3WAKE_BURST_MS (9'b111110011),
.USB_LFPS_TPERIOD (4'b0011),
.USB_LFPS_TPERIOD_ACCURATE (1'b1),
.USB_MODE (1'b0),
.USB_PCIE_ERR_REP_DIS (1'b0),
.USB_PING_SATA_MAX_INIT (21),
.USB_PING_SATA_MIN_INIT (12),
.USB_POLL_SATA_MAX_BURST (8),
.USB_POLL_SATA_MIN_BURST (4),
.USB_RAW_ELEC (1'b0),
.USB_RXIDLE_P0_CTRL (1'b1),
.USB_TXIDLE_TUNE_ENABLE (1'b1),
.USB_U1_SATA_MAX_WAKE (7),
.USB_U1_SATA_MIN_WAKE (4),
.USB_U2_SAS_MAX_COM (64),
.USB_U2_SAS_MIN_COM (36),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.Y_ALL_MODE (1'b0))
i_gtye4_channel (
.CDRSTEPDIR (1'b0),
.CDRSTEPSQ (1'b0),
.CDRSTEPSX (1'b0),
.CFGRESET (1'b0),
.CLKRSVD0 (1'b0),
.CLKRSVD1 (1'b0),
.CPLLFREQLOCK (1'b0),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'b1),
.CPLLPD (up_cpll_rst),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (1'b0),
.DMONFIFORESET (1'b0),
.DMONITORCLK (1'b0),
.DRPADDR (up_addr_int[9:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPEN (up_enb_int),
.DRPRST (1'd0),
.DRPWE (up_wr_int),
.EYESCANRESET (up_es_reset),
.EYESCANTRIGGER (1'b0),
.FREQOS (1'b0),
.GTGREFCLK (1'b0),
.GTNORTHREFCLK0 (1'b0),
.GTNORTHREFCLK1 (1'b0),
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'b0),
.GTRSVD (16'b0000000000000000),
.GTRXRESET (up_rx_rst),
.GTRXRESETSEL (1'b0),
.GTSOUTHREFCLK0 (1'b0),
.GTSOUTHREFCLK1 (1'b0),
.GTTXRESET (up_tx_rst),
.GTTXRESETSEL (1'b0),
.GTYRXN (rx_n),
.GTYRXP (rx_p),
.INCPCTRL (1'b0),
.LOOPBACK (3'b000),
.PCIEEQRXEQADAPTDONE (1'b0),
.PCIERSTIDLE (1'b0),
.PCIERSTTXSYNCSTART (1'b0),
.PCIEUSERRATEDONE (1'b0),
.PCSRSVDIN (16'b0000000000000000),
.QPLL0CLK (qpll2ch_clk),
.QPLL0FREQLOCK (1'b0),
.QPLL0REFCLK (qpll2ch_ref_clk),
.QPLL1CLK (qpll1_clk),
.QPLL1FREQLOCK (1'b0),
.QPLL1REFCLK (qpll1_ref_clk),
.RESETOVRD (1'b0),
.RX8B10BEN (RX8B10BEN),
.RXAFECFOKEN (1'b1),
.RXBUFRESET (1'b0),
.RXCDRFREQRESET (1'b0),
.RXCDRHOLD (1'b0),
.RXCDROVRDEN (1'b0),
.RXCDRRESET (1'b0),
.RXCHBONDEN (1'b0),
.RXCHBONDI (5'b00000),
.RXCHBONDLEVEL (3'b000),
.RXCHBONDMASTER (1'b0),
.RXCHBONDSLAVE (1'b0),
.RXCKCALRESET (1'b0),
.RXCKCALSTART (7'b0000000),
.RXCOMMADETEN (1'b1),
.RXDFEAGCHOLD (1'b0),
.RXDFEAGCOVRDEN (1'b0),
.RXDFECFOKFCNUM (4'b1101),
.RXDFECFOKFEN (1'b0),
.RXDFECFOKFPULSE (1'b0),
.RXDFECFOKHOLD (1'b0),
.RXDFECFOKOVREN (1'b0),
.RXDFEKHHOLD (1'b0),
.RXDFEKHOVRDEN (1'b0),
.RXDFELFHOLD (1'b0),
.RXDFELFOVRDEN (1'b0),
.RXDFELPMRESET (1'b0),
.RXDFETAP10HOLD (1'b0),
.RXDFETAP10OVRDEN (1'b0),
.RXDFETAP11HOLD (1'b0),
.RXDFETAP11OVRDEN (1'b0),
.RXDFETAP12HOLD (1'b0),
.RXDFETAP12OVRDEN (1'b0),
.RXDFETAP13HOLD (1'b0),
.RXDFETAP13OVRDEN (1'b0),
.RXDFETAP14HOLD (1'b0),
.RXDFETAP14OVRDEN (1'b0),
.RXDFETAP15HOLD (1'b0),
.RXDFETAP15OVRDEN (1'b0),
.RXDFETAP2HOLD (1'b0),
.RXDFETAP2OVRDEN (1'b0),
.RXDFETAP3HOLD (1'b0),
.RXDFETAP3OVRDEN (1'b0),
.RXDFETAP4HOLD (1'b0),
.RXDFETAP4OVRDEN (1'b0),
.RXDFETAP5HOLD (1'b0),
.RXDFETAP5OVRDEN (1'b0),
.RXDFETAP6HOLD (1'b0),
.RXDFETAP6OVRDEN (1'b0),
.RXDFETAP7HOLD (1'b0),
.RXDFETAP7OVRDEN (1'b0),
.RXDFETAP8HOLD (1'b0),
.RXDFETAP8OVRDEN (1'b0),
.RXDFETAP9HOLD (1'b0),
.RXDFETAP9OVRDEN (1'b0),
.RXDFEUTHOLD (1'b0),
.RXDFEUTOVRDEN (1'b0),
.RXDFEVPHOLD (1'b0),
.RXDFEVPOVRDEN (1'b0),
.RXDFEXYDEN (1'b0),
.RXDLYBYPASS (1'b1),
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (1'b0),
.RXELECIDLEMODE (2'b11),
.RXEQTRAINING (1'b0),
.RXGEARBOXSLIP (rx_bitslip_s),
.RXLATCLK (1'b0),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMGCHOLD (1'b0),
.RXLPMGCOVRDEN (1'b0),
.RXLPMHFHOLD (1'b0),
.RXLPMHFOVRDEN (1'b0),
.RXLPMLFHOLD (1'b0),
.RXLPMLFKLOVRDEN (1'b0),
.RXLPMOSHOLD (1'b0),
.RXLPMOSOVRDEN (1'b0),
.RXMCOMMAALIGNEN (rx_calign),
.RXMONITORSEL (2'b00),
.RXOOBRESET (1'b0),
.RXOSCALRESET (1'b0),
.RXOSHOLD (1'b0),
.RXOSOVRDEN (1'b0),
.RXOUTCLKSEL (up_rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'b0),
.RXPD (2'b0),
.RXPHALIGN (1'b0),
.RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b0),
.RXPHDLYRESET (1'b0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'b0),
.RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (rx_prbscntreset),
.RXPRBSSEL (rx_prbssel),
2021-05-18 10:26:43 +00:00
.RXPROGDIVRESET (up_rx_rst),
.RXRATE (rx_rate_m2),
.RXRATEMODE (1'b0),
.RXSLIDE (1'b0),
.RXSLIPOUTCLK (1'b0),
.RXSLIPPMA (1'b0),
.RXSYNCALLIN (1'b0),
.RXSYNCIN (1'b0),
.RXSYNCMODE (1'b0),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXTERMINATION (1'b0),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_usrclk),
.RXUSRCLK2 (rx_usrclk2),
.SIGVALIDCLK (1'b0),
.TSTIN (20'b00000000000000000000),
2021-05-10 15:12:38 +00:00
.TX8B10BBYPASS (8'b0),
.TX8B10BEN (TX8B10BEN),
.TXCOMINIT (1'b0),
.TXCOMSAS (1'b0),
.TXCOMWAKE (1'b0),
.TXCTRL0 (16'b0000000000000000),
.TXCTRL1 (16'b0000000000000000),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA (tx_data_s),
.TXDATAEXTENDRSVD (8'b00000000),
.TXDCCFORCESTART (1'b0),
.TXDCCRESET (1'b0),
.TXDEEMPH (2'b00),
.TXDETECTRX (1'b0),
.TXDIFFCTRL (up_tx_diffctrl),
.TXDLYBYPASS (1'b1),
.TXDLYEN (1'b0),
.TXDLYHOLD (1'b0),
.TXDLYOVRDEN (1'b0),
.TXDLYSRESET (1'b0),
.TXDLYUPDOWN (1'b0),
.TXELECIDLE (1'b0),
.TXHEADER ({4'b0,tx_header}),
.TXINHIBIT (1'b0),
.TXLATCLK (1'b0),
.TXLFPSTRESET (1'b0),
.TXLFPSU2LPEXIT (1'b0),
.TXLFPSU3WAKE (1'b0),
.TXMAINCURSOR (7'b1010000),
.TXMARGIN (3'b000),
.TXMUXDCDEXHOLD (1'b0),
.TXMUXDCDORWREN (1'b0),
.TXONESZEROS (1'b0),
.TXOUTCLKSEL (up_tx_out_clk_sel),
.TXPCSRESET (1'b0),
.TXPD (2'b0),
.TXPDELECIDLEMODE (1'b0),
.TXPHALIGN (1'b0),
.TXPHALIGNEN (1'b0),
.TXPHDLYPD (1'b1),
.TXPHDLYRESET (1'b0),
.TXPHDLYTSTCLK (1'b0),
.TXPHINIT (1'b0),
.TXPHOVRDEN (1'b0),
.TXPIPPMEN (1'b0),
.TXPIPPMOVRDEN (1'b0),
.TXPIPPMPD (1'b0),
.TXPIPPMSEL (1'b0),
.TXPIPPMSTEPSIZE (5'b00000),
.TXPISOPD (1'b0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'b0),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor),
.TXPRBSFORCEERR (tx_prbsforceerr),
.TXPRBSSEL (tx_prbssel),
.TXPRECURSOR (up_tx_precursor),
.TXPROGDIVRESET (up_tx_rst),
.TXRATE (tx_rate_m2),
.TXRATEMODE (1'b0),
.TXSEQUENCE (7'b0000000),
.TXSWING (1'b0),
.TXSYNCALLIN (1'b0),
.TXSYNCIN (1'b0),
.TXSYNCMODE (1'b0),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_usrclk),
.TXUSRCLK2 (tx_usrclk2),
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLREFCLKLOST (),
.DMONITOROUT (),
.DMONITOROUTCLK (),
.DRPDO (up_rdata_s),
.DRPRDY (up_ready_s),
.EYESCANDATAERROR (),
.GTPOWERGOOD (),
.GTREFCLKMONITOR (),
.GTYTXN (tx_n),
.GTYTXP (tx_p),
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
.PCIEUSERRATESTART (),
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
.POWERPRESENT (),
.RESETEXCEPTION (),
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCDRLOCK (),
.RXCDRPHDONE (),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCHBONDO (),
.RXCKCALDONE (),
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
.RXCTRL2 (),
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA (rx_data_s),
.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXHEADER (rx_header_s),
.RXHEADERVALID (),
.RXLFPSTRESETDET (),
.RXLFPSU2LPEXITDET (),
.RXLFPSU3WAKEDET (),
.RXMONITOROUT (),
.RXOSINTDONE (),
.RXOSINTSTARTED (),
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
.RXOUTCLK (rx_out_clk_s),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXPHALIGNDONE (),
.RXPHALIGNERR (),
.RXPMARESETDONE (),
.RXPRBSERR (rx_prbserr),
.RXPRBSLOCKED (rx_prbslocked),
.RXPRGDIVRESETDONE (),
.RXRATEDONE (),
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done_s),
.RXSLIDERDY (),
.RXSLIPDONE (),
.RXSLIPOUTCLKRDY (),
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
.RXSYNCDONE (),
.RXSYNCOUT (),
.RXVALID (),
.TXBUFSTATUS (),
.TXCOMFINISH (),
.TXDCCDONE (),
.TXDLYSRESETDONE (),
.TXOUTCLK (tx_out_clk_s),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXPHALIGNDONE (),
.TXPHINITDONE (),
.TXPMARESETDONE (),
.TXPRGDIVRESETDONE (),
.TXRATEDONE (),
.TXRESETDONE (tx_rst_done_s),
.TXSYNCDONE (),
.TXSYNCOUT ()
);
end
endgenerate
endmodule
2016-06-14 16:18:56 +00:00
// ***************************************************************************
// ***************************************************************************