2023-07-10 08:36:06 +00:00
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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2023-01-18 12:36:47 +00:00
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create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
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create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}]
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create_clock -period "122.07 ns" -name adc_clk [get_ports {adc_clk_in}]
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derive_pll_clocks
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derive_clock_uncertainty
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set input_clock_period 30.51; # Period of input clock fMAX_DCLK=32.768MHz
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set hold_time 8.5;
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set setup_time 8.5;
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set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay;
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set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay;
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