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pluto_hdl_adi/projects/fmcomms5/zc702/system_bd.tcl

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Tcl
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moved fmcomms5
2014-05-19 17:49:49 +00:00
source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
fmcomms5: Update UP instantiations
2017-04-21 12:10:44 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 150.0
fmcomms5/zc702: Fix the sys_dma_clk connections
2020-04-15 13:27:45 +00:00
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
set sys_dma_clk [get_bd_nets sys_dma_clk]
fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform
2015-04-02 19:29:17 +00:00
source ../common/fmcomms5_bd.tcl
ad9361- delay initialization
2017-03-15 16:06:49 +00:00
fmcomms5: Update UP instantiations
2017-04-21 12:10:44 +00:00
ad_ip_parameter axi_ad9361_0 CONFIG.ADC_INIT_DELAY 24
ad_ip_parameter axi_ad9361_1 CONFIG.ADC_INIT_DELAY 24
fmcomms5_zc702: Enable AXI_SLICE for the DMA This will increase the timing margin for the design
2018-07-18 11:19:56 +00:00
ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 1
ad9361- delay initialization
2017-03-15 16:06:49 +00:00