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pluto_hdl_adi/projects/ad9208_dual_ebz/vcu118/system_bd.tcl

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ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
## FIFO depth is 4Mb - 250k samples (65k samples per converter)
set adc_fifo_address_width 13
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source ../common/dual_ad9208_bd.tcl
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
foreach i {0 1} {
ad_ip_parameter util_adc_${i}_xcvr CONFIG.RX_CLK25_DIV 30
ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_CFG0 0x1fa
ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_CFG1 0x2b
ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_CFG2 0x2
ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_FBDIV 2
ad9208_dual_ebz/vcu118: remove GTY prefix from parameters
2019-11-14 13:23:21 +00:00
ad_ip_parameter util_adc_${i}_xcvr CONFIG.CH_HSPMUX 0x4040
ad_ip_parameter util_adc_${i}_xcvr CONFIG.PREIQ_FREQ_BST 1
ad_ip_parameter util_adc_${i}_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_adc_${i}_xcvr CONFIG.RXPI_CFG0 0x3002
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_CFG0 0x333c
ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_CFG4 0x2
ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_FBDIV 20
ad9208_dual_ebz/vcu118: remove GTY prefix from parameters
2019-11-14 13:23:21 +00:00
ad_ip_parameter util_adc_${i}_xcvr CONFIG.PPF0_CFG 0xB00
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
}