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pluto_hdl_adi/projects/daq2/zc706/system_bd.tcl

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Tcl
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daq2: initial checkin
2014-06-12 19:54:25 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
daq2: register map updates
2014-07-03 16:36:37 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
plddr3: internal buswidth/clock conversion
2014-11-12 19:43:02 +00:00
p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
plddr3: internal buswidth/clock conversion
2014-11-12 19:43:02 +00:00
plddr3: sys-rst from board pushbutton
2014-12-15 17:59:04 +00:00
create_bd_port -dir I -type rst sys_rst
daq2/zc706: base system updates
2015-03-09 20:09:54 +00:00
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
plddr3: internal buswidth/clock conversion
2014-11-12 19:43:02 +00:00
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
daq2/zc706: base system updates
2015-03-09 20:09:54 +00:00
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
daq2/zc706: base system updates
2015-03-09 20:09:54 +00:00
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
axi_adcfifo: added
2015-04-07 20:21:39 +00:00
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
daq2/zc706: base system updates
2015-03-09 20:09:54 +00:00
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
plddr3: internal buswidth/clock conversion
2014-11-12 19:43:02 +00:00
daq2: initial checkin
2014-06-12 19:54:25 +00:00
source ../common/daq2_bd.tcl