pluto_hdl_adi/library/common/ad_dds_sine.v

// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************
// this is a sine function (approximate), the basic idea is to approximate sine as a
// polynomial function (there are a lot of stuff about this on the web)

`timescale 1ns/100ps

module ad_dds_sine (

  // sine = sin(angle)

  clk,
  angle,
  sine,
  ddata_in,
  ddata_out);

  // parameters

  parameter   DELAY_DATA_WIDTH = 16;
  localparam  DW = DELAY_DATA_WIDTH - 1;

  // sine = sin(angle)

  input           clk;
  input   [15:0]  angle;
  output  [15:0]  sine;
  input   [DW:0]  ddata_in;
  output  [DW:0]  ddata_out;

  // internal registers

  reg     [DW:0]  ddata_s2_i = 'd0;
  reg             data_msb_s2_i = 'd0;
  reg     [15:0]  data_delay_s2_i = 'd0;
  reg     [15:0]  data_sine_s2_i = 'd0;
  reg     [DW:0]  ddata_s2 = 'd0;
  reg             data_msb_s2 = 'd0;
  reg     [15:0]  data_sine_s2 = 'd0;
  reg     [DW:0]  ddata_s3_i = 'd0;
  reg             data_msb_s3_i = 'd0;
  reg     [15:0]  data_delay_s3_i = 'd0;
  reg     [15:0]  data_sine_s3_i = 'd0;
  reg     [DW:0]  ddata_s4 = 'd0;
  reg             data_msb = 'd0;
  reg     [14:0]  data_sine_p = 'd0;
  reg     [14:0]  data_sine_n = 'd0;
  reg     [DW:0]  ddata_out = 'd0;
  reg     [15:0]  sine = 'd0;

  // internal signals

  wire    [DW:0]  ddata_s1_s;
  wire            data_msb_s1_s;
  wire    [31:0]  data_sine_s1_s;
  wire    [DW:0]  ddata_s2_i_s;
  wire            data_msb_s2_i_s;
  wire    [15:0]  data_delay_s2_i_s;
  wire    [31:0]  data_sine_s2_i_s;
  wire    [DW:0]  ddata_s2_s;
  wire            data_msb_s2_s;
  wire    [31:0]  data_sine_s2_s;
  wire    [DW:0]  ddata_s3_i_s;
  wire            data_msb_s3_i_s;
  wire    [15:0]  data_delay_s3_i_s;
  wire    [31:0]  data_sine_s3_i_s;
  wire    [DW:0]  ddata_s3_s;
  wire            data_msb_s3_s;
  wire    [31:0]  data_sine_s3_s;

  // level 1 (intermediate) A*x;

  ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s1 (
    .clk (clk),
    .data_a ({1'b0, angle[14:0]}),
    .data_b (16'hc90f),
    .data_p (data_sine_s1_s),
    .ddata_in ({ddata_in, angle[15]}),
    .ddata_out ({ddata_s1_s, data_msb_s1_s}));

  // level 1, (final) B*x;

  ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2_i (
    .clk (clk),
    .data_a (data_sine_s1_s[30:15]),
    .data_b (16'h19f0),
    .data_p (data_sine_s2_i_s),
    .ddata_in ({ddata_s1_s, data_msb_s1_s, data_sine_s1_s[30:15]}),
    .ddata_out ({ddata_s2_i_s, data_msb_s2_i_s, data_delay_s2_i_s}));

  // level 2 inputs, B*x and (1-A*x)

  always @(posedge clk) begin
    ddata_s2_i <= ddata_s2_i_s;
    data_msb_s2_i <= data_msb_s2_i_s;
    data_delay_s2_i <= data_delay_s2_i_s;
    data_sine_s2_i <= 16'ha2f9 - data_sine_s2_i_s[28:13];
  end

  // level 2, second order (A*x2 + B*x)

  ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s2 (
    .clk (clk),
    .data_a (data_delay_s2_i),
    .data_b (data_sine_s2_i),
    .data_p (data_sine_s2_s),
    .ddata_in ({ddata_s2_i, data_msb_s2_i}),
    .ddata_out ({ddata_s2_s, data_msb_s2_s}));

  always @(posedge clk) begin
    ddata_s2 <= ddata_s2_s;
    data_msb_s2 <= data_msb_s2_s;
    if (data_sine_s2_s[31:29] == 0) begin
      data_sine_s2 <= data_sine_s2_s[28:13];
    end else begin
      data_sine_s2 <= 16'hffff;
    end
  end

  // level 2, intermediate (B*y)

  ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s3_i (
    .clk (clk),
    .data_a (data_sine_s2),
    .data_b (16'h3999),
    .data_p (data_sine_s3_i_s),
    .ddata_in ({ddata_s2, data_msb_s2, data_sine_s2}),
    .ddata_out ({ddata_s3_i_s, data_msb_s3_i_s, data_delay_s3_i_s}));

  always @(posedge clk) begin
    ddata_s3_i <= ddata_s3_i_s;
    data_msb_s3_i <= data_msb_s3_i_s;
    data_delay_s3_i <= data_delay_s3_i_s;
    data_sine_s3_i <= 16'hc666 + data_sine_s3_i_s[31:16];
  end

  // level 2, second order (A*y2 + B*y)

  ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s3 (
    .clk (clk),
    .data_a (data_delay_s3_i),
    .data_b (data_sine_s3_i),
    .data_p (data_sine_s3_s),
    .ddata_in ({ddata_s3_i, data_msb_s3_i}),
    .ddata_out ({ddata_s3_s, data_msb_s3_s}));

  always @(posedge clk) begin
    ddata_s4 <= ddata_s3_s;
    data_msb <= data_msb_s3_s;
    data_sine_p <= data_sine_s3_s[31:17];
    data_sine_n <= ~data_sine_s3_s[31:17] + 1'b1;
    ddata_out <= ddata_s4;
    sine <= (data_msb == 1'b1) ? {1'b1, data_sine_n} : {1'b0, data_sine_p};
  end

endmodule

// ***************************************************************************
// ***************************************************************************