pluto_hdl_adi/library/axi_ad9361/axi_ad9361_tx_dds.v

// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module axi_ad9361_tx_dds (

  // dac interface

  dac_clk,
  dac_rst,
  dac_dds_data,

  // processor interface

  dac_dds_enable,
  dac_dds_data_enable,
  dac_dds_format,
  dac_dds_pattenb,
  dac_dds_patt_1,
  dac_dds_init_1,
  dac_dds_incr_1,
  dac_dds_scale_1,
  dac_dds_patt_2,
  dac_dds_init_2,
  dac_dds_incr_2,
  dac_dds_scale_2);

  // parameters

  parameter DP_DISABLE = 0;

  // dac interface

  input           dac_clk;
  input           dac_rst;
  output  [15:0]  dac_dds_data;

  // processor interface

  input           dac_dds_enable;
  input           dac_dds_data_enable;
  input           dac_dds_format;
  input           dac_dds_pattenb;
  input   [15:0]  dac_dds_patt_1;
  input   [15:0]  dac_dds_init_1;
  input   [15:0]  dac_dds_incr_1;
  input   [15:0]  dac_dds_scale_1;
  input   [15:0]  dac_dds_patt_2;
  input   [15:0]  dac_dds_init_2;
  input   [15:0]  dac_dds_incr_2;
  input   [15:0]  dac_dds_scale_2;

  // internal registers

  reg     [15:0]  dac_dds_phase_0 = 'd0;
  reg     [15:0]  dac_dds_phase_1 = 'd0;
  reg             dac_dds_datasel = 'd0;
  reg     [15:0]  dac_dds_data = 'd0;

  // internal signals

  wire    [15:0]  dac_dds_data_s;

  // dds phase counters

  always @(posedge dac_clk) begin
    if (dac_dds_enable == 1'b0) begin
      dac_dds_phase_0 <= dac_dds_init_1;
      dac_dds_phase_1 <= dac_dds_init_2;
    end else if (dac_dds_data_enable == 1'b1) begin
      dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_1;
      dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_2;
    end
  end

  // output is either 2's complement or offset binary.

  always @(posedge dac_clk) begin
    if (dac_dds_data_enable == 1'b1) begin
      dac_dds_datasel <= ~dac_dds_datasel;
      if (dac_dds_pattenb == 1'b0) begin
        dac_dds_data <= dac_dds_data_s;
      end else if (dac_dds_datasel == 1'b1) begin
        dac_dds_data <= dac_dds_patt_2;
      end else begin
        dac_dds_data <= dac_dds_patt_1;
      end
    end
  end

  // dds

  generate
  if (DP_DISABLE == 1) begin
  assign dac_dds_data_s = 16'd0;
  end else begin
  ad_dds i_dds_0 (
    .clk (dac_clk),
    .dds_format (dac_dds_format),
    .dds_enable (dac_dds_enable),
    .dds_phase_0 (dac_dds_phase_0),
    .dds_scale_0 (dac_dds_scale_1),
    .dds_phase_1 (dac_dds_phase_1),
    .dds_scale_1 (dac_dds_scale_2),
    .dds_data (dac_dds_data_s));
  end
  endgenerate

endmodule

// ***************************************************************************
// ***************************************************************************