2015-05-11 14:17:07 +00:00
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2015-06-01 14:59:33 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2015-05-11 14:17:07 +00:00
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derive_pll_clocks
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2015-07-13 14:07:18 +00:00
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derive_clock_uncertainty
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2015-05-11 14:17:07 +00:00
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2017-06-06 20:09:15 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
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set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
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set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]
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2017-05-15 13:32:36 +00:00
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