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pluto_hdl_adi/library/axi_ad9963/axi_ad9963_ip.tcl

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axi_ad9963: Initial commit
2017-01-31 14:18:58 +00:00
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9963
adi_ip_files axi_ad9963 [list \
library: Update scripts with new constraints Update all IPs tcl scripts with the new constraints files. Refer to commit 335fef0.
2017-03-30 13:12:07 +00:00
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
axi_ad9963: Initial commit
2017-01-31 14:18:58 +00:00
"$ad_hdl_dir/library/common/ad_rst.v" \
library & projects- ad_lvds/ad_data replace
2017-07-26 14:31:48 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
Move Xilinx specific DC filter implementation to library/xilinx/common/ The DC filter implementation in library/common/dc_filter.v is Xilinx specific as it uses the Xilinx DSP48 hard-macro. There is a matching Altera specific implementation in library/altera/common/dc_filter.v. Move the Xilinx specific implementation from the generic common folder to the Xilinx specific common folder in library/xilinx/common/ since that is where all other Xilinx specific common modules reside. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:31:50 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
axi_ad9963: Initial commit
2017-01-31 14:18:58 +00:00
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
axi_ad9963: Integrated ADC/DAC clock enables
2017-04-18 09:24:42 +00:00
"axi_ad9963_constr.xdc" \
axi_ad9963: Initial commit
2017-01-31 14:18:58 +00:00
"axi_ad9963_if.v" \
"axi_ad9963_rx_pnmon.v" \
"axi_ad9963_rx_channel.v" \
"axi_ad9963_rx.v" \
"axi_ad9963_tx_channel.v" \
"axi_ad9963_tx.v" \
"axi_ad9963.v" ]
adi_ip_properties axi_ad9963
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
axi_ad9963: Fix port dependency definition
2017-11-29 12:40:47 +00:00
adi_set_ports_dependency "delay_clk" \
"(spirit:decode(id('MODELPARAM_VALUE.ADC_IODELAY_ENABLE')) = 1)" 0
axi_ad9963: Disable delay_clk port when IODELAYs are unused The delay_clk is only used internally when the IODELAYs are enabled. This means the port has no function when the IODELAYs are disabled so hide the port in that case. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-06 17:51:52 +00:00
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
axi_ad9963: Initial commit
2017-01-31 14:18:58 +00:00
ipx::save_core [ipx::current_core]