77 lines
3.2 KiB
Coq
77 lines
3.2 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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/*
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* Helper module for synchronizing bit signals from one clock domain to another.
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* It uses the standard approach of 2 FF in series.
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* Note, that while the module allows to synchronize multiple bits at once it is
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* only able to synchronize multi-bit signals where at max one bit changes per
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* clock cycle (e.g. a gray counter).
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*/
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module sync_bits
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(
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input [NUM_BITS-1:0] in,
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input out_resetn,
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input out_clk,
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output [NUM_BITS-1:0] out
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);
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// Number of bits to synchronize
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parameter NUM_BITS = 1;
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// Whether input and output clocks are asynchronous, if 0 the synchronizer will
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// be bypassed and the output signal equals the input signal.
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parameter CLK_ASYNC = 1;
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reg [NUM_BITS-1:0] out_m1 = 'h0;
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reg [NUM_BITS-1:0] out_m2 = 'h0;
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always @(posedge out_clk)
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begin
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if (out_resetn == 1'b0) begin
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out_m1 <= 'b0;
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out_m2 <= 'b0;
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end else begin
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out_m1 <= in;
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out_m2 <= out_m1;
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end
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end
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assign out = CLK_ASYNC ? out_m2 : in;
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endmodule
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