pluto_hdl_adi/projects/fmcjesdadc1/a5gt/system_constr.sdc

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2014-04-01 15:46:37 +00:00
2015-06-24 09:30:03 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name ref_clk_250mhz [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx_clk}]
2014-04-01 15:46:37 +00:00
derive_pll_clocks
derive_clock_uncertainty