2016-08-16 12:50:46 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2017-08-22 20:26:57 +00:00
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create_clock -period "8.138 ns" -name ref_clk0 [get_ports {ref_clk0}]
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create_clock -period "8.138 ns" -name ref_clk1 [get_ports {ref_clk1}]
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2016-08-16 12:50:46 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2017-06-07 13:19:03 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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2016-08-16 12:50:46 +00:00
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2017-06-07 13:19:03 +00:00
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if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} {
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set_max_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.150
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set_min_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.000
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}
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