pluto_hdl_adi/projects/daq3/common/daq3_bd.tcl

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Tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# dac peripherals
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ad_ip_instance axi_adxcvr axi_ad9152_xcvr
ad_ip_parameter axi_ad9152_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9152_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9152_xcvr CONFIG.TX_OR_RX_N 1
adi_axi_jesd204_tx_create axi_ad9152_jesd 4
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ad_ip_instance axi_ad9152 axi_ad9152_core
ad_ip_instance util_upack axi_ad9152_upack
ad_ip_parameter axi_ad9152_upack CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter axi_ad9152_upack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_dmac axi_ad9152_dma
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9152_dma CONFIG.ID 1
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST 128
# adc peripherals
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ad_ip_instance axi_adxcvr axi_ad9680_xcvr
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
adi_axi_jesd204_rx_create axi_ad9680_jesd 4
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ad_ip_instance axi_ad9680 axi_ad9680_core
ad_ip_instance util_cpack axi_ad9680_cpack
ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# shared transceiver core
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ad_ip_instance util_adxcvr util_daq3_xcvr
ad_ip_parameter util_daq3_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_daq3_xcvr CONFIG.TX_NUM_OF_LANES 4
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV_RATIO 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
ad_ip_parameter util_daq3_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_daq3_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
ad_ip_parameter util_daq3_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020
ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn
ad_connect sys_cpu_clk util_daq3_xcvr/up_clk
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# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
ad_xcvrpll tx_ref_clk_0 util_daq3_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_daq3_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
# connections (dac)
ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1}
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
ad_connect axi_ad9152_jesd/tx_data_tdata axi_ad9152_core/tx_data
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk
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ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0
ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0
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ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
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ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
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ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk
ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst
ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk
ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn
ad_connect axi_ad9152_fifo/bypass GND
}
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ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_fifo/dac_rst
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ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid
ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data
ad_connect axi_ad9152_core/dac_dunf axi_ad9152_fifo/dac_dunf
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ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data
ad_connect axi_ad9152_fifo/dma_valid axi_ad9152_dma/m_axis_valid
ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last
# connections (adc)
ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core/rx_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_core/rx_data
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
}
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr
ad_cpu_interconnect 0x44A00000 axi_ad9152_core
ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9680_core
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9152_dma/m_src_axi
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
}
# interrupts
ad_cpu_interrupt ps-10 mb-15 axi_ad9152_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
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ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq