2016-09-09 15:04:41 +00:00
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2016-09-12 14:30:28 +00:00
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package require -exact qsys 14.0
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2016-09-09 15:04:41 +00:00
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2016-09-12 14:30:28 +00:00
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set_module_property NAME alt_serdes
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set_module_property DESCRIPTION "Altera SERDES"
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2016-09-09 15:04:41 +00:00
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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2016-09-12 14:30:28 +00:00
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set_module_property DISPLAY_NAME alt_serdes
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set_module_property COMPOSITION_CALLBACK p_alt_serdes
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2016-09-09 15:04:41 +00:00
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2016-09-12 14:30:28 +00:00
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# parameters
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2016-09-09 15:04:41 +00:00
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2016-09-12 14:30:28 +00:00
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add_parameter MODE STRING "CLK"
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2016-09-09 15:04:41 +00:00
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set_parameter_property MODE DISPLAY_NAME MODE
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set_parameter_property MODE TYPE STRING
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set_parameter_property MODE UNITS None
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2016-09-12 14:30:28 +00:00
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set_parameter_property MODE HDL_PARAMETER false
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set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"}
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add_parameter DDR_OR_SDR_N INTEGER 1
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set_parameter_property DDR_OR_SDR_N DISPLAY_NAME DDR_OR_SDR_N
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set_parameter_property DDR_OR_SDR_N TYPE INTEGER
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set_parameter_property DDR_OR_SDR_N UNITS None
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set_parameter_property DDR_OR_SDR_N HDL_PARAMETER false
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set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
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add_parameter SERDES_FACTOR INTEGER 8
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set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR
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set_parameter_property SERDES_FACTOR TYPE INTEGER
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set_parameter_property SERDES_FACTOR UNITS None
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set_parameter_property SERDES_FACTOR HDL_PARAMETER false
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set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
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add_parameter CLKIN_FREQUENCY FLOAT 500.0
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set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY
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set_parameter_property CLKIN_FREQUENCY TYPE FLOAT
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set_parameter_property CLKIN_FREQUENCY UNITS None
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set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
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set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
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2016-10-25 17:19:39 +00:00
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED false
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2016-09-12 14:30:28 +00:00
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proc p_alt_serdes {} {
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set m_mode [get_parameter_value "MODE"]
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set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
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set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
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set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
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2016-10-25 17:19:39 +00:00
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set m_device_family [get_parameter_value DEVICE_FAMILY]
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2016-09-12 14:30:28 +00:00
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set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
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set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
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2016-10-27 13:40:45 +00:00
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2016-10-11 14:09:39 +00:00
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set m_ls_phase 22.5
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set m_ld_phase 315.0
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set m_ld_duty_cycle 12.5
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2016-09-12 14:30:28 +00:00
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if {$m_serdes_factor == 4} {
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2016-10-11 14:09:39 +00:00
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set m_ls_phase 45
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set m_ld_phase 270.0
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set m_ld_duty_cycle 25.0
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2016-09-09 15:04:41 +00:00
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}
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2016-10-27 13:40:45 +00:00
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## arria 10, serdes clock, data-in and data-out
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if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
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add_instance alt_serdes_pll altera_iopll
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set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
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set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
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set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
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set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
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set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
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add_interface rst reset sink
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set_interface_property rst EXPORT_OF alt_serdes_pll.reset
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF alt_serdes_pll.locked
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
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add_interface hs_clk conduit end
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set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
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add_interface ls_clk clock source
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set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
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add_instance alt_serdes_pll_reconfig altera_pll_reconfig
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add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
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add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
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add_interface drp_clk clock sink
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set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
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add_interface drp_rst reset sink
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set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
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add_interface pll_reconfig avalon slave
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set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
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2016-09-12 14:30:28 +00:00
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}
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2016-09-09 15:04:41 +00:00
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2016-10-27 13:40:45 +00:00
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if {($m_mode == "IN") && ($m_device_family == "Arria 10")} {
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2016-09-12 14:30:28 +00:00
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2016-09-13 14:39:54 +00:00
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add_instance alt_serdes_in altera_lvds
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set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO}
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2016-09-12 14:30:28 +00:00
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set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
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2016-09-12 15:45:23 +00:00
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set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor
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2016-09-12 14:30:28 +00:00
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set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
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2016-09-12 15:45:23 +00:00
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set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
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add_interface data_in conduit end
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set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in
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2016-09-13 14:39:54 +00:00
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add_interface clk conduit end
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2016-09-12 15:45:23 +00:00
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set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden
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2016-09-13 14:39:54 +00:00
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add_interface div_clk conduit end
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2016-09-12 15:45:23 +00:00
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set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out
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add_interface delay_locked conduit end
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set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
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2016-09-12 14:30:28 +00:00
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}
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2016-09-09 15:04:41 +00:00
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2016-10-27 13:40:45 +00:00
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if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} {
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2016-09-12 14:30:28 +00:00
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2016-09-13 14:39:54 +00:00
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add_instance alt_serdes_out altera_lvds
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2016-09-12 14:30:28 +00:00
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set_instance_parameter_value alt_serdes_out {MODE} {TX}
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set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
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2016-09-12 15:45:23 +00:00
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set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor
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2016-09-14 16:05:48 +00:00
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set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
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2016-09-12 15:45:23 +00:00
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set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
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2016-09-12 14:30:28 +00:00
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set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
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2016-09-12 15:45:23 +00:00
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add_interface data_out conduit end
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set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
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2016-09-13 14:39:54 +00:00
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add_interface clk conduit end
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2016-09-12 15:45:23 +00:00
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set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden
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2016-09-13 14:39:54 +00:00
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add_interface div_clk conduit end
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2016-09-12 15:45:23 +00:00
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set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
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2016-09-12 14:30:28 +00:00
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}
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2016-10-27 13:40:45 +00:00
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## cyclone v, serdes clock, data-in and data-out
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if {($m_mode == "CLK") && ($m_device_family == "Cyclone V")} {
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add_instance alt_serdes_pll altera_pll
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set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
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set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
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set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
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add_interface rst reset sink
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set_interface_property rst EXPORT_OF alt_serdes_pll.reset
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF alt_serdes_pll.locked
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add_interface hs_clk clock source
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set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
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add_interface loaden clock source
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set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
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add_interface ls_clk clock source
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set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
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add_instance alt_serdes_pll_reconfig altera_pll_reconfig
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add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
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add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
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add_interface drp_clk clock sink
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set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
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add_interface drp_rst reset sink
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set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
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add_interface pll_reconfig avalon slave
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set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
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}
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2016-09-12 14:30:28 +00:00
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}
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2016-10-27 13:40:45 +00:00
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