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pluto_hdl_adi/projects/ad6676evb/common/ad6676evb_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad6676evb: Convert to ADI JESD204 Convert the AD6676EVB project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:56:41 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# adc peripherals
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_adxcvr axi_ad6676_xcvr
ad_ip_parameter axi_ad6676_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad6676_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad6676_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad6676_xcvr CONFIG.LPM_OR_DFE_N 0
ad6676: Fix OUT_CLK_SEL configuration The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as binary numbers. But the tools will interpret them as decimal number resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter values as decimal values to avoid this. This is not a critical issue since software will overwrite this setting at system boot-up. But it should be fixed anyway. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:08:00 +00:00
ad_ip_parameter axi_ad6676_xcvr CONFIG.SYS_CLK_SEL 0x0
ad_ip_parameter axi_ad6676_xcvr CONFIG.OUT_CLK_SEL 0x4
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad6676evb: Convert to ADI JESD204 Convert the AD6676EVB project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:56:41 +00:00
adi_axi_jesd204_rx_create axi_ad6676_jesd 2
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_ad6676 axi_ad6676_core
ad6766evb: Use new pack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:06:43 +00:00
ad_ip_instance util_cpack2 axi_ad6676_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_dmac axi_ad6676_dma
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad6676_dma CONFIG.ID 0
ad_ip_parameter axi_ad6676_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad6676_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad6676_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad6676_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_DATA_WIDTH_DEST 64
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
# transceiver core
ad6676evb: Updated project to 2015.2.1 - updated to the new jesd framework - added cpack core
2015-09-25 11:44:46 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance util_adxcvr util_ad6676_xcvr
ad_ip_parameter util_ad6676_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_ad6676_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_ad6676_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_NUM_OF_LANES 2
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_CLK25_DIV 8
ad6676evb: Fix RX_DFE_LPM_CFG parameter, as the design is used in DFE mode The parameter RX_DFE_LPM_CFG should be 0x954 for DFE and 0x904 in LPM I've removed also QPLL_FBDIV parameter, as QPLL is not used in this design
2018-02-27 17:15:23 +00:00
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_DFE_LPM_CFG 0x0954
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
# reference clocks & resets
create_bd_port -dir I rx_ref_clk_0
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
create_bd_port -dir O rx_core_clk
ad6676evb: Updated project to 2015.2.1 - updated to the new jesd framework - added cpack core
2015-09-25 11:44:46 +00:00
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_cpll_rst_*
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn util_ad6676_xcvr/up_rstn
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk util_ad6676_xcvr/up_clk
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (adc)
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
ad_connect util_ad6676_xcvr/rx_out_clk_0 rx_core_clk
ad6676evb: Convert to ADI JESD204 Convert the AD6676EVB project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:56:41 +00:00
ad_connect axi_ad6676_jesd/rx_sof axi_ad6676_core/rx_sof
ad_connect axi_ad6676_jesd/rx_data_tdata axi_ad6676_core/rx_data
ad6766evb: Use new pack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:06:43 +00:00
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/clk
ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/reset
ad_connect axi_ad6676_core/adc_dovf axi_ad6676_cpack/fifo_wr_overflow
ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/fifo_wr_en
for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad6676_core/adc_enable_${i} axi_ad6676_cpack/enable_${i}
ad_connect axi_ad6676_core/adc_data_${i} axi_ad6676_cpack/fifo_wr_data_${i}
}
projects/ad6676-adrv9371: xcvr updates
2016-11-23 16:06:22 +00:00
ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk
ad6766evb: Use new pack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-12 18:06:43 +00:00
ad_connect axi_ad6676_dma/fifo_wr axi_ad6676_cpack/packed_fifo_wr
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (cpu)
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad6676_core
ad6676evb: Convert to ADI JESD204 Convert the AD6676EVB project to the ADI JESD204 link layer core. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:56:41 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad6676_jesd
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interconnect 0x7c420000 axi_ad6676_dma
ad6676: Update projects to xcvr frame work
2016-11-09 14:47:31 +00:00
# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad6676_xcvr/m_axi
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (adc)
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad6676_dma/m_dest_axi
ad6676evb: DMA should use $sys_dma_resetn
2019-06-12 15:25:09 +00:00
ad_connect $sys_dma_resetn axi_ad6676_dma/m_dest_axi_aresetn
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interrupts
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-12 mb-12 axi_ad6676_jesd/irq
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_cpu_interrupt ps-13 mb-13 axi_ad6676_dma/irq