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pluto_hdl_adi/projects/cftl_std/common/cftl_std_bd.tcl

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cftl_xil_zed: Initial commit for common platform used with CFTL circuits This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selects
2015-01-09 15:41:24 +00:00
# cftl
cftl_std: Update project to the new framework
2015-03-23 14:03:15 +00:00
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_cftl
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cftl
cftl_xil_zed: Initial commit for common platform used with CFTL circuits This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selects
2015-01-09 15:41:24 +00:00
cftl_std: Update project to the new framework
2015-03-23 14:03:15 +00:00
# iic
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 12:11:33 +00:00
cftl_std: ip automatic version update
2017-04-14 13:53:10 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1
cftl_xil_zed: Initial commit for common platform used with CFTL circuits This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selects
2015-01-09 15:41:24 +00:00
# iic cftl
cftl_std: Update project to the new framework
2015-03-23 14:03:15 +00:00
ad_connect iic_cftl sys_ps7/IIC_0