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axi_dac_interpolate: Initial commit
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// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
license: Add some clarification to the header license
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
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// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
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//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
axi_dac_interpolate: Initial commit
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//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
axi_dac_interpolate: Initial commit
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//
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// OR
//
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
axi_dac_interpolate: Initial commit
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
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module axi_dac_interpolate #(
parameter CORRECTION_DISABLE = 1) (
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input dac_clk,
axi_dac_interpolate: Make dac_reset external
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input dac_rst,
axi_dac_interpolate: Initial commit
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input [15:0] dac_data_a,
input [15:0] dac_data_b,
input dac_valid_a,
input dac_valid_b,
axi_dac_interpolate: Fix channel sync mechanism The previous channel sync mechanism was simply holding the transmission by pulling down the dma_rd_en of the two DMAs for each channel(set reg 0x50). After a period of time (that will take the two DMAs to have the data ready to move) the dma_rd_en was set for both channels, resulting in a synchronized start. This mechanism is valid when the two channels are streaming the same type of data (constant, waveform, buffer or math) at close frequencies. Streaming 10MHz on a channel and 100KHz on the second one will result in different interpolation factors being used for the two channels. The interpolation counter runs only when the dma_transfer_suspended(reg 0x50) is cleared. Because of this, different delays are added by the interpolation counter one DMA with continuous dma_rd_en will have data earlier than the one with dma_rd_en controlled by the interpolation counter. Furthermore, because the interpolation counter value is not reset at each dma_transfer_suspended, the phase shift between the 2 channels will differ at each start of transmission. To make the transfer start synced immune to the above irregularities a sync_transfer_start register was added (bit 1 of the 0x50 reg). When this bit is set and the bit 0(dma_transfer_suspended) is toggled, the interpolation counters are reset. Each channel enables it's DMA until valid data is received, then it waits for the adjacent channel to get valid data. This mechanism will be simplified in a future update by using a streaming interface between the axi_dac_interpolate and the DMAs that does not require the probing of the DMA.
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input dma_valid_a,
input dma_valid_b,
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
output [15:0] dac_int_data_a,
output [15:0] dac_int_data_b,
output dac_int_valid_a,
output dac_int_valid_b,
axi_dac_interpolate: Initial commit
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// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
axi_dac_interpolate: Reduce AXI address width The axi_dac_interpolate does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
axi_dac_interpolate: Reduce AXI address width The axi_dac_interpolate does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-10 17:30:19 +00:00
input [ 6:0] s_axi_araddr,
axi_dac_interpolate: Initial commit
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input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal signals
wire up_clk;
wire up_rstn;
axi_dac_interpolate: Reduce AXI address width The axi_dac_interpolate does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-10 17:30:19 +00:00
wire [ 4:0] up_waddr;
axi_dac_interpolate: Initial commit
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wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
axi_dac_interpolate: Reduce AXI address width The axi_dac_interpolate does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-10 17:30:19 +00:00
wire [ 4:0] up_raddr;
axi_dac_interpolate: Initial commit
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wire [31:0] interpolation_ratio_a;
wire [31:0] interpolation_ratio_b;
axi_dac_interpolate: Reduce filter_mask signal width Only the lower 3 bits of the filter_mask signal are used, no need to keep the other bits around. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-10 08:50:02 +00:00
wire [ 2:0] filter_mask_a;
wire [ 2:0] filter_mask_b;
axi_dac_interpolate: Initial commit
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wire dma_transfer_suspend;
axi_dac_interpolate: Fix channel sync mechanism The previous channel sync mechanism was simply holding the transmission by pulling down the dma_rd_en of the two DMAs for each channel(set reg 0x50). After a period of time (that will take the two DMAs to have the data ready to move) the dma_rd_en was set for both channels, resulting in a synchronized start. This mechanism is valid when the two channels are streaming the same type of data (constant, waveform, buffer or math) at close frequencies. Streaming 10MHz on a channel and 100KHz on the second one will result in different interpolation factors being used for the two channels. The interpolation counter runs only when the dma_transfer_suspended(reg 0x50) is cleared. Because of this, different delays are added by the interpolation counter one DMA with continuous dma_rd_en will have data earlier than the one with dma_rd_en controlled by the interpolation counter. Furthermore, because the interpolation counter value is not reset at each dma_transfer_suspended, the phase shift between the 2 channels will differ at each start of transmission. To make the transfer start synced immune to the above irregularities a sync_transfer_start register was added (bit 1 of the 0x50 reg). When this bit is set and the bit 0(dma_transfer_suspended) is toggled, the interpolation counters are reset. Each channel enables it's DMA until valid data is received, then it waits for the adjacent channel to get valid data. This mechanism will be simplified in a future update by using a streaming interface between the axi_dac_interpolate and the DMAs that does not require the probing of the DMA.
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wire start_sync_channels;
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
wire dac_correction_enable_a;
wire dac_correction_enable_b;
wire [15:0] dac_correction_coefficient_a;
wire [15:0] dac_correction_coefficient_b;
axi_dac_interpolate: Initial commit
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// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
axi_dac_interpolate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE))
i_filter_a (
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.dac_clk (dac_clk),
.dac_rst (dac_rst),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.dac_data (dac_data_a),
.dac_valid (dac_valid_a),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.dac_int_data (dac_int_data_a),
.dac_int_valid (dac_int_valid_a),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.filter_mask (filter_mask_a),
.interpolation_ratio (interpolation_ratio_a),
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
.dma_transfer_suspend (dma_transfer_suspend),
axi_dac_interpolate: Fix channel sync mechanism The previous channel sync mechanism was simply holding the transmission by pulling down the dma_rd_en of the two DMAs for each channel(set reg 0x50). After a period of time (that will take the two DMAs to have the data ready to move) the dma_rd_en was set for both channels, resulting in a synchronized start. This mechanism is valid when the two channels are streaming the same type of data (constant, waveform, buffer or math) at close frequencies. Streaming 10MHz on a channel and 100KHz on the second one will result in different interpolation factors being used for the two channels. The interpolation counter runs only when the dma_transfer_suspended(reg 0x50) is cleared. Because of this, different delays are added by the interpolation counter one DMA with continuous dma_rd_en will have data earlier than the one with dma_rd_en controlled by the interpolation counter. Furthermore, because the interpolation counter value is not reset at each dma_transfer_suspended, the phase shift between the 2 channels will differ at each start of transmission. To make the transfer start synced immune to the above irregularities a sync_transfer_start register was added (bit 1 of the 0x50 reg). When this bit is set and the bit 0(dma_transfer_suspended) is toggled, the interpolation counters are reset. Each channel enables it's DMA until valid data is received, then it waits for the adjacent channel to get valid data. This mechanism will be simplified in a future update by using a streaming interface between the axi_dac_interpolate and the DMAs that does not require the probing of the DMA.
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.start_sync_channels (start_sync_channels),
.dma_valid (dma_valid_a),
.dma_valid_adjacent (dma_valid_b),
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
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.dac_correction_enable(dac_correction_enable_a),
.dac_correction_coefficient(dac_correction_coefficient_a)
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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);
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
axi_dac_interpolate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE))
i_filter_b (
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.dac_clk (dac_clk),
.dac_rst (dac_rst),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.dac_data (dac_data_b),
.dac_valid (dac_valid_b),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.dac_int_data (dac_int_data_b),
.dac_int_valid (dac_int_valid_b),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
.filter_mask (filter_mask_b),
.interpolation_ratio (interpolation_ratio_b),
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
.dma_transfer_suspend (dma_transfer_suspend),
axi_dac_interpolate: Fix channel sync mechanism The previous channel sync mechanism was simply holding the transmission by pulling down the dma_rd_en of the two DMAs for each channel(set reg 0x50). After a period of time (that will take the two DMAs to have the data ready to move) the dma_rd_en was set for both channels, resulting in a synchronized start. This mechanism is valid when the two channels are streaming the same type of data (constant, waveform, buffer or math) at close frequencies. Streaming 10MHz on a channel and 100KHz on the second one will result in different interpolation factors being used for the two channels. The interpolation counter runs only when the dma_transfer_suspended(reg 0x50) is cleared. Because of this, different delays are added by the interpolation counter one DMA with continuous dma_rd_en will have data earlier than the one with dma_rd_en controlled by the interpolation counter. Furthermore, because the interpolation counter value is not reset at each dma_transfer_suspended, the phase shift between the 2 channels will differ at each start of transmission. To make the transfer start synced immune to the above irregularities a sync_transfer_start register was added (bit 1 of the 0x50 reg). When this bit is set and the bit 0(dma_transfer_suspended) is toggled, the interpolation counters are reset. Each channel enables it's DMA until valid data is received, then it waits for the adjacent channel to get valid data. This mechanism will be simplified in a future update by using a streaming interface between the axi_dac_interpolate and the DMAs that does not require the probing of the DMA.
2019-08-05 07:44:21 +00:00
.start_sync_channels (start_sync_channels),
.dma_valid (dma_valid_b),
.dma_valid_adjacent (dma_valid_a),
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
.dac_correction_enable(dac_correction_enable_b),
.dac_correction_coefficient(dac_correction_coefficient_b)
axi_dac_interpolate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. Also since the filter is two instances of the same logic, one for each channel, let the new sub-module model one channel and instantiate it twice. This allows to change the implementation without having to change the same code twice. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-05 12:23:14 +00:00
);
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
.clk (dac_clk),
.dac_interpolation_ratio_a (interpolation_ratio_a),
.dac_filter_mask_a (filter_mask_a),
.dac_interpolation_ratio_b (interpolation_ratio_b),
.dac_filter_mask_b (filter_mask_b),
.dma_transfer_suspend (dma_transfer_suspend),
axi_dac_interpolate: Fix channel sync mechanism The previous channel sync mechanism was simply holding the transmission by pulling down the dma_rd_en of the two DMAs for each channel(set reg 0x50). After a period of time (that will take the two DMAs to have the data ready to move) the dma_rd_en was set for both channels, resulting in a synchronized start. This mechanism is valid when the two channels are streaming the same type of data (constant, waveform, buffer or math) at close frequencies. Streaming 10MHz on a channel and 100KHz on the second one will result in different interpolation factors being used for the two channels. The interpolation counter runs only when the dma_transfer_suspended(reg 0x50) is cleared. Because of this, different delays are added by the interpolation counter one DMA with continuous dma_rd_en will have data earlier than the one with dma_rd_en controlled by the interpolation counter. Furthermore, because the interpolation counter value is not reset at each dma_transfer_suspended, the phase shift between the 2 channels will differ at each start of transmission. To make the transfer start synced immune to the above irregularities a sync_transfer_start register was added (bit 1 of the 0x50 reg). When this bit is set and the bit 0(dma_transfer_suspended) is toggled, the interpolation counters are reset. Each channel enables it's DMA until valid data is received, then it waits for the adjacent channel to get valid data. This mechanism will be simplified in a future update by using a streaming interface between the axi_dac_interpolate and the DMAs that does not require the probing of the DMA.
2019-08-05 07:44:21 +00:00
.start_sync_channels (start_sync_channels),
axi_dac_interpolate: Add correction at the begining of the interpolation chain The CIC filter introduces different amplifications depending on the interpolation ratio. By adding a multiplier in the interpolation chain the amplification can be compensated
2017-08-03 14:06:47 +00:00
.dac_correction_enable_a(dac_correction_enable_a),
.dac_correction_enable_b(dac_correction_enable_b),
.dac_correction_coefficient_a(dac_correction_coefficient_a),
.dac_correction_coefficient_b(dac_correction_coefficient_b),
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
axi_dac_interpolate: Reduce AXI address width The axi_dac_interpolate does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-10 17:30:19 +00:00
up_axi #(
up_axi_update: ADDRESS_WIDTH parameter is now a localparam ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2; up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-15 15:16:07 +00:00
.AXI_ADDRESS_WIDTH(7)
axi_dac_interpolate: Reduce AXI address width The axi_dac_interpolate does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-10 17:30:19 +00:00
) i_up_axi (
axi_dac_interpolate: Initial commit
2017-01-31 14:22:49 +00:00
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************