24 lines
358 B
Coq
24 lines
358 B
Coq
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module util_sync_reset (
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input async_resetn,
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input clk,
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output sync_resetn
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);
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// Keep it asserted for three clock cycles
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reg [2:0] reset = 3'b111;
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assign sync_resetn = reset[2];
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always @(posedge clk or negedge async_resetn) begin
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if (async_resetn == 1'b0) begin
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reset <= 3'b111;
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end else begin
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reset <= {reset[1:0], 1'b0};
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end
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end
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endmodule
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