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pluto_hdl_adi/projects/daq3/kcu105/system_bd.tcl

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daq3/kcu105: copy
2015-12-10 14:41:47 +00:00
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## FIFO depth is 4Mb - 250k samples
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## FIFO depth is 4Mb - 250k samples
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00
set dac_fifo_name axi_ad9152_fifo
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
set dac_fifo_address_width 15
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00
set dac_data_width 128
set dac_dma_data_width 128
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## NOTE: With this configuration the #36Kb BRAM utilization is at ~70%
daq3/kcu105: copy
2015-12-10 14:41:47 +00:00
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
file renamed; sed output; fingers crossed
2017-02-22 20:56:37 +00:00
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
daq3/kcu105: updates
2015-12-14 14:29:48 +00:00
source ../common/daq3_bd.tcl
daq3/kcu105: copy
2015-12-10 14:41:47 +00:00
daq3/kcu105: Define transceiver type as Ultrascale When software configures the system it takes into account the transceiver type. By default, the XCVR_TYPE is 0 for 7 Series.
2018-03-20 16:38:25 +00:00
ad_ip_parameter axi_ad9152_xcvr CONFIG.XCVR_TYPE 1
ad_ip_parameter axi_ad9680_xcvr CONFIG.XCVR_TYPE 1
daq3: Update IP instantiations
2017-04-21 12:07:41 +00:00
ad_ip_parameter util_daq3_xcvr CONFIG.XCVR_TYPE 1
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
daq3/kcu105: copy
2015-12-10 14:41:47 +00:00