39 lines
1.9 KiB
Plaintext
39 lines
1.9 KiB
Plaintext
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set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set ad9361_clk [get_clocks -of_objects [get_ports clk]]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay \
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-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $ad9361_clk]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay \
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-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay \
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-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
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