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pluto_hdl_adi/library/axi_dmac/tb/dma_read_tb

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axi_dmac: Add transfer testbenches Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-07 12:56:33 +00:00
#!/bin/bash
SOURCE="dma_read_tb.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
axi_dmac: Split transfer handling into separate sub-module Move the transfer logic, including the 2d module, into its own sub-module. This allows testing of the full transfer logic independently of the register map logic. The top-level module now only instantiates the register map and transfer module, but does not have any logic on its own. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
axi_dmac: Add transfer testbenches Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-07 12:56:33 +00:00
SOURCE+=" ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../dest_fifo_inf.v"
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v ../../util_axis_fifo/address_gray_pipelined.v"
SOURCE+=" ../../common/ad_mem.v"
SOURCE+=" ../../util_cdc/sync_bits.v ../../util_cdc/sync_gray.v"
SOURCE+=" ../../util_axis_resize/util_axis_resize.v"
cd `dirname $0`
source run_tb.sh