2018-03-23 11:55:11 +00:00
|
|
|
####################################################################################
|
2023-02-07 11:30:08 +00:00
|
|
|
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
2021-09-13 20:50:01 +00:00
|
|
|
## SPDX short identifier: BSD-1-Clause
|
2018-03-23 11:55:11 +00:00
|
|
|
####################################################################################
|
|
|
|
|
|
|
|
# Assumes this file is in library/scripts/library.mk
|
|
|
|
HDL_LIBRARY_PATH := $(subst scripts/library.mk,,$(lastword $(MAKEFILE_LIST)))
|
|
|
|
|
2018-03-25 07:21:37 +00:00
|
|
|
include $(HDL_LIBRARY_PATH)../quiet.mk
|
|
|
|
|
2019-03-14 13:50:21 +00:00
|
|
|
CASE_INCLUDE := $(wildcard temporary_case_dependencies.mk)
|
|
|
|
ifneq ($(CASE_INCLUDE),)
|
|
|
|
include temporary_case_dependencies.mk
|
|
|
|
endif
|
|
|
|
|
2018-03-23 11:55:11 +00:00
|
|
|
VIVADO := vivado -mode batch -source
|
|
|
|
|
2019-03-14 13:50:21 +00:00
|
|
|
CLEAN_TARGET += *.cache
|
2018-03-23 11:55:11 +00:00
|
|
|
CLEAN_TARGET += *.data
|
|
|
|
CLEAN_TARGET += *.xpr
|
|
|
|
CLEAN_TARGET += *.log
|
|
|
|
CLEAN_TARGET += component.xml
|
|
|
|
CLEAN_TARGET += *.jou
|
|
|
|
CLEAN_TARGET += xgui
|
2023-02-07 11:30:08 +00:00
|
|
|
CLEAN_TARGET += gui
|
|
|
|
CLEAN_TARGET += *.runs
|
|
|
|
CLEAN_TARGET += *.gen
|
2018-03-23 11:55:11 +00:00
|
|
|
CLEAN_TARGET += *.ip_user_files
|
|
|
|
CLEAN_TARGET += *.srcs
|
|
|
|
CLEAN_TARGET += *.hw
|
|
|
|
CLEAN_TARGET += *.sim
|
|
|
|
CLEAN_TARGET += .Xil
|
2018-08-13 13:59:02 +00:00
|
|
|
CLEAN_TARGET += .timestamp_intel
|
2021-02-09 10:29:26 +00:00
|
|
|
CLEAN_TARGET += *.hbs
|
2022-09-23 12:07:45 +00:00
|
|
|
CLEAN_TARGET += tb/*.log
|
|
|
|
CLEAN_TARGET += tb/*.xml
|
|
|
|
CLEAN_TARGET += tb/*.jou
|
|
|
|
CLEAN_TARGET += tb/*.dir
|
|
|
|
CLEAN_TARGET += tb/*.pb
|
|
|
|
CLEAN_TARGET += tb/*.vcd
|
|
|
|
CLEAN_TARGET += tb/*.wdb
|
|
|
|
CLEAN_TARGET += tb/dcv.
|
|
|
|
CLEAN_TARGET += tb/vsim.wlf
|
|
|
|
CLEAN_TARGET += tb/work
|
|
|
|
CLEAN_TARGET += tb/vcd
|
|
|
|
CLEAN_TARGET += tb/run
|
|
|
|
CLEAN_TARGET += tb/libraries
|
|
|
|
CLEAN_TARGET += tb/.Xil
|
|
|
|
CLEAN_TARGET += tb/xsim_gui_cmd.tcl
|
|
|
|
CLEAN_TARGET += tb/libraries
|
2018-03-23 11:55:11 +00:00
|
|
|
|
2022-07-12 11:06:15 +00:00
|
|
|
GENERIC_DEPS += $(HDL_LIBRARY_PATH)../scripts/adi_env.tcl
|
2018-03-23 11:55:11 +00:00
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
.PHONY: all intel intel_dep xilinx xilinx_dep clean clean-all
|
2018-03-23 11:55:11 +00:00
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
all: intel xilinx
|
2018-03-23 11:55:11 +00:00
|
|
|
|
|
|
|
clean: clean-all
|
|
|
|
|
|
|
|
clean-all:
|
2018-03-25 07:21:37 +00:00
|
|
|
$(call clean, \
|
|
|
|
$(CLEAN_TARGET), \
|
|
|
|
$(HL)$(LIBRARY_NAME)$(NC) library)
|
2018-03-23 11:55:11 +00:00
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
ifneq ($(INTEL_DEPS),)
|
2018-03-27 09:21:09 +00:00
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
INTEL_DEPS += $(GENERIC_DEPS)
|
|
|
|
INTEL_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_intel.tcl
|
|
|
|
INTEL_DEPS += $(foreach dep,$(INTEL_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/.timestamp_intel)
|
2018-03-27 09:21:09 +00:00
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
intel: intel_dep .timestamp_intel
|
2018-03-27 09:21:09 +00:00
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
.timestamp_intel: $(INTEL_DEPS)
|
2018-03-27 09:21:09 +00:00
|
|
|
touch $@
|
|
|
|
|
2018-08-13 13:59:02 +00:00
|
|
|
intel_dep:
|
|
|
|
@for lib in $(INTEL_LIB_DEPS); do \
|
|
|
|
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} intel || exit $$?; \
|
2018-03-27 09:21:09 +00:00
|
|
|
done
|
|
|
|
endif
|
|
|
|
|
|
|
|
ifneq ($(XILINX_DEPS),)
|
|
|
|
|
|
|
|
XILINX_DEPS += $(GENERIC_DEPS)
|
2018-08-13 13:59:02 +00:00
|
|
|
XILINX_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_xilinx.tcl
|
2018-03-27 09:21:09 +00:00
|
|
|
XILINX_DEPS += $(foreach dep,$(XILINX_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
|
|
|
|
|
|
|
|
xilinx: xilinx_dep component.xml
|
|
|
|
|
|
|
|
component.xml: $(XILINX_DEPS)
|
2018-03-23 11:55:11 +00:00
|
|
|
-rm -rf $(CLEAN_TARGET)
|
2018-03-25 07:21:37 +00:00
|
|
|
$(call build, \
|
|
|
|
$(VIVADO) $(LIBRARY_NAME)_ip.tcl, \
|
|
|
|
$(LIBRARY_NAME)_ip.log, \
|
|
|
|
$(HL)$(LIBRARY_NAME)$(NC) library)
|
2018-03-23 11:55:11 +00:00
|
|
|
|
2018-03-27 09:21:09 +00:00
|
|
|
xilinx_dep:
|
|
|
|
@for lib in $(XILINX_LIB_DEPS); do \
|
|
|
|
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} xilinx || exit $$?; \
|
2018-03-23 11:55:11 +00:00
|
|
|
done
|
2018-03-27 09:21:09 +00:00
|
|
|
@for intf in $(XILINX_INTERFACE_DEPS); do \
|
|
|
|
$(MAKE) -C $(HDL_LIBRARY_PATH)$${intf} xilinx || exit $$?; \
|
2018-03-23 11:55:11 +00:00
|
|
|
done
|
2018-03-27 09:21:09 +00:00
|
|
|
endif
|