505 lines
17 KiB
Coq
505 lines
17 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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output fan_tach,
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output fan_pwrm,
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input i2s_sdata_in,
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output i2s_sdata_out,
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output i2s_mclk,
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output i2s_bclk,
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output i2s_lrclk,
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inout pmod0_d0,
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inout pmod0_d1,
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inout pmod0_d2,
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inout pmod0_d3,
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inout pmod0_d4,
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inout pmod0_d5,
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inout pmod0_d6,
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inout pmod0_d7,
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output led_gpio_0,
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output led_gpio_1,
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output led_gpio_2,
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output led_gpio_3,
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inout dip_gpio_0,
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inout dip_gpio_1,
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inout dip_gpio_2,
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inout dip_gpio_3,
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inout pb_gpio_0,
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inout pb_gpio_1,
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inout pb_gpio_2,
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inout pb_gpio_3,
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output resetb_ad9545,
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output hmc7044_car_reset,
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inout hmc7044_car_gpio_1,
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inout hmc7044_car_gpio_2,
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inout hmc7044_car_gpio_3,
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inout hmc7044_car_gpio_4,
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output spi_csn_hmc7044_car,
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inout i2c0_scl,
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inout i2c0_sda,
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inout i2c1_scl,
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inout i2c1_sda,
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input oscout_p,
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input oscout_n,
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input ref_clk_a_p,
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input ref_clk_a_n,
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input core_clk_a_p,
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input core_clk_a_n,
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input [ 3:0] rx_data_a_p,
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input [ 3:0] rx_data_a_n,
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output [ 3:0] tx_data_a_p,
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output [ 3:0] tx_data_a_n,
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output rx_sync_a_p,
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output rx_sync_a_n,
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output rx_os_sync_a_p,
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output rx_os_sync_a_n,
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input tx_sync_a_p,
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input tx_sync_a_n,
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input tx_sync_a_1_p,
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input tx_sync_a_1_n,
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input sysref_a_p,
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input sysref_a_n,
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inout adrv9009_tx1_enable_a,
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inout adrv9009_tx2_enable_a,
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inout adrv9009_rx1_enable_a,
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inout adrv9009_rx2_enable_a,
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inout adrv9009_test_a,
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inout adrv9009_reset_b_a,
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inout adrv9009_gpint_a,
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inout adrv9009_gpio_00_a,
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inout adrv9009_gpio_01_a,
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inout adrv9009_gpio_02_a,
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inout adrv9009_gpio_03_a,
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inout adrv9009_gpio_04_a,
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inout adrv9009_gpio_05_a,
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inout adrv9009_gpio_06_a,
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inout adrv9009_gpio_07_a,
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inout adrv9009_gpio_15_a,
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inout adrv9009_gpio_08_a,
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inout adrv9009_gpio_09_a,
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inout adrv9009_gpio_10_a,
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inout adrv9009_gpio_11_a,
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inout adrv9009_gpio_12_a,
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inout adrv9009_gpio_14_a,
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inout adrv9009_gpio_13_a,
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inout adrv9009_gpio_17_a,
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inout adrv9009_gpio_16_a,
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inout adrv9009_gpio_18_a,
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input ref_clk_b_p,
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input ref_clk_b_n,
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input core_clk_b_p,
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input core_clk_b_n,
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input [ 3:0] rx_data_b_p,
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input [ 3:0] rx_data_b_n,
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output [ 3:0] tx_data_b_p,
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output [ 3:0] tx_data_b_n,
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output rx_sync_b_p,
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output rx_sync_b_n,
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output rx_os_sync_b_p,
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output rx_os_sync_b_n,
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input tx_sync_b_p,
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input tx_sync_b_n,
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input tx_sync_b_1_p,
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input tx_sync_b_1_n,
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input sysref_b_p,
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input sysref_b_n,
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inout adrv9009_tx1_enable_b,
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inout adrv9009_tx2_enable_b,
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inout adrv9009_rx1_enable_b,
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inout adrv9009_rx2_enable_b,
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inout adrv9009_test_b,
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inout adrv9009_reset_b_b,
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inout adrv9009_gpint_b,
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inout adrv9009_gpio_00_b,
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inout adrv9009_gpio_01_b,
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inout adrv9009_gpio_02_b,
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inout adrv9009_gpio_03_b,
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inout adrv9009_gpio_04_b,
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inout adrv9009_gpio_05_b,
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inout adrv9009_gpio_06_b,
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inout adrv9009_gpio_07_b,
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inout adrv9009_gpio_15_b,
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inout adrv9009_gpio_08_b,
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inout adrv9009_gpio_09_b,
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inout adrv9009_gpio_10_b,
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inout adrv9009_gpio_11_b,
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inout adrv9009_gpio_12_b,
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inout adrv9009_gpio_14_b,
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inout adrv9009_gpio_13_b,
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inout adrv9009_gpio_17_b,
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inout adrv9009_gpio_16_b,
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inout adrv9009_gpio_18_b,
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output hmc7044_reset,
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output hmc7044_sync,
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inout hmc7044_gpio_1,
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inout hmc7044_gpio_2,
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inout hmc7044_gpio_3,
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inout hmc7044_gpio_4,
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output spi_csn_adrv9009_a,
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output spi_csn_adrv9009_b,
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output spi_csn_hmc7044,
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input ddr4_ref_1_clk_n,
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input ddr4_ref_1_clk_p,
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output ddr4_rtl_1_act_n,
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output [16:0] ddr4_rtl_1_adr,
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output [1:0] ddr4_rtl_1_ba,
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output [0:0] ddr4_rtl_1_bg,
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output [0:0] ddr4_rtl_1_ck_c,
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output [0:0] ddr4_rtl_1_ck_t,
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output [0:0] ddr4_rtl_1_cke,
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output [0:0] ddr4_rtl_1_cs_n,
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inout [3:0] ddr4_rtl_1_dm_n,
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inout [31:0] ddr4_rtl_1_dq,
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inout [3:0] ddr4_rtl_1_dqs_c,
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inout [3:0] ddr4_rtl_1_dqs_t,
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output [0:0] ddr4_rtl_1_odt,
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output ddr4_rtl_1_reset_n,
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output ddr4_rtl_1_par,
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input ddr4_rtl_1_alert_n,
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output spi_clk,
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inout spi_sdio,
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input spi_miso
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);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire [2:0] spi_csn;
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wire ref_clk_a;
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wire core_clk_a;
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wire rx_sync_rx;
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wire tx_sync_a;
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wire sysref_a;
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wire ref_clk_b;
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wire core_clk_b;
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wire rx_sync_obs;
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wire rx_os_sync_b;
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wire tx_sync_b;
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wire sysref_b;
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wire tx_sync;
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wire spi_mosi;
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wire spi0_miso;
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reg [7:0] spi_3_to_8_csn;
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always @(*) begin
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case (spi_csn)
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3'h0: spi_3_to_8_csn = 8'b11111110;
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3'h1: spi_3_to_8_csn = 8'b11111101;
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3'h2: spi_3_to_8_csn = 8'b11111011;
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3'h3: spi_3_to_8_csn = 8'b11110111;
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default: spi_3_to_8_csn = 8'b11111111;
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endcase
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end
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assign spi_csn_adrv9009_a = spi_3_to_8_csn[0];
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assign spi_csn_adrv9009_b = spi_3_to_8_csn[1];
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assign spi_csn_hmc7044 = spi_3_to_8_csn[2];
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assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
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adrv9009_zu11eg_som_spi i_spi (
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.spi_csn(spi_3_to_8_csn),
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.spi_clk(spi_clk),
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.spi_mosi(spi_mosi),
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.spi_miso_i(spi_miso),
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.spi_miso_o(spi0_miso),
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.spi_sdio(spi_sdio));
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assign tx_sync = tx_sync_a & tx_sync_b;
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assign gpio_i[94:90] = gpio_o[94:90];
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assign gpio_i[31:28] = gpio_o[31:28];
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ad_iobuf #(.DATA_WIDTH(58)) i_iobuf (
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.dio_t ({gpio_t[89:32]}),
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.dio_i ({gpio_o[89:32]}),
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.dio_o ({gpio_i[89:32]}),
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.dio_p ({
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hmc7044_gpio_4, // 89
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hmc7044_gpio_3, // 88
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hmc7044_gpio_1, // 87
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hmc7044_gpio_2, // 86
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hmc7044_sync, // 85
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hmc7044_reset, // 84
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adrv9009_tx2_enable_b, // 83
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adrv9009_tx1_enable_b, // 82
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adrv9009_rx2_enable_b, // 81
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adrv9009_rx1_enable_b, // 80
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adrv9009_test_b, // 79
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adrv9009_reset_b_b, // 78
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adrv9009_gpint_b, // 77
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adrv9009_gpio_18_b, // 77
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adrv9009_gpio_17_b, // 75
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adrv9009_gpio_16_b, // 74
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adrv9009_gpio_15_b, // 73
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adrv9009_gpio_14_b, // 72
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adrv9009_gpio_13_b, // 71
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adrv9009_gpio_12_b, // 70
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adrv9009_gpio_11_b, // 69
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adrv9009_gpio_10_b, // 68
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adrv9009_gpio_09_b, // 67
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adrv9009_gpio_08_b, // 66
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adrv9009_gpio_07_b, // 65
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adrv9009_gpio_06_b, // 64
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adrv9009_gpio_05_b, // 63
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adrv9009_gpio_04_b, // 62
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adrv9009_gpio_03_b, // 61
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adrv9009_gpio_02_b, // 60
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adrv9009_gpio_01_b, // 58
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adrv9009_gpio_00_b, // 58
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adrv9009_tx2_enable_a, // 57
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adrv9009_tx1_enable_a, // 56
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adrv9009_rx2_enable_a, // 55
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adrv9009_rx1_enable_a, // 54
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adrv9009_test_a, // 53
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adrv9009_reset_b_a, // 52
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adrv9009_gpint_a, // 51
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adrv9009_gpio_18_a, // 50
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adrv9009_gpio_17_a, // 49
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adrv9009_gpio_16_a, // 48
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adrv9009_gpio_15_a, // 47
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adrv9009_gpio_14_a, // 46
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adrv9009_gpio_13_a, // 45
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adrv9009_gpio_12_a, // 44
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adrv9009_gpio_11_a, // 43
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adrv9009_gpio_10_a, // 42
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adrv9009_gpio_09_a, // 41
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adrv9009_gpio_08_a, // 40
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adrv9009_gpio_07_a, // 39
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adrv9009_gpio_06_a, // 38
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adrv9009_gpio_05_a, // 37
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adrv9009_gpio_04_a, // 36
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adrv9009_gpio_03_a, // 35
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adrv9009_gpio_02_a, // 34
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||
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adrv9009_gpio_01_a, // 33
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adrv9009_gpio_00_a})); // 32
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ad_iobuf #(.DATA_WIDTH(28)) i_carrier_iobuf (
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||
|
|
.dio_t ({gpio_t[27:0]}),
|
||
|
|
.dio_i ({gpio_o[27:0]}),
|
||
|
|
.dio_o ({gpio_i[27:0]}),
|
||
|
|
.dio_p ({
|
||
|
|
hmc7044_car_gpio_3, // 27
|
||
|
|
hmc7044_car_gpio_2, // 26
|
||
|
|
hmc7044_car_gpio_1, // 25
|
||
|
|
hmc7044_car_gpio_0, // 24
|
||
|
|
hmc7044_car_reset, // 23
|
||
|
|
resetb_ad9545, // 22
|
||
|
|
fan_tach, // 21
|
||
|
|
fan_pwrm, // 20
|
||
|
|
pmod0_d7, // 19
|
||
|
|
pmod0_d6, // 18
|
||
|
|
pmod0_d5, // 17
|
||
|
|
pmod0_d4, // 16
|
||
|
|
pmod0_d3, // 15
|
||
|
|
pmod0_d2, // 14
|
||
|
|
pmod0_d1, // 13
|
||
|
|
pmod0_d0, // 12
|
||
|
|
led_gpio_3, // 11
|
||
|
|
led_gpio_2, // 10
|
||
|
|
led_gpio_1, // 9
|
||
|
|
led_gpio_0, // 8
|
||
|
|
dip_gpio_3, // 7
|
||
|
|
dip_gpio_2, // 6
|
||
|
|
dip_gpio_1, // 5
|
||
|
|
dip_gpio_0, // 4
|
||
|
|
pb_gpio_3, // 3
|
||
|
|
pb_gpio_2, // 2
|
||
|
|
pb_gpio_1, // 1
|
||
|
|
pb_gpio_0})); // 0
|
||
|
|
|
||
|
|
IBUFDS_GTE4 i_ibufds_ref_clk_1 (
|
||
|
|
.CEB (1'd0),
|
||
|
|
.I (ref_clk_a_p),
|
||
|
|
.IB (ref_clk_a_n),
|
||
|
|
.O (ref_clk_a),
|
||
|
|
.ODIV2 ());
|
||
|
|
|
||
|
|
IBUFDS_GTE4 i_ibufds_ref_clk_2 (
|
||
|
|
.CEB (1'd0),
|
||
|
|
.I (ref_clk_b_p),
|
||
|
|
.IB (ref_clk_b_n),
|
||
|
|
.O (ref_clk_b),
|
||
|
|
.ODIV2 ());
|
||
|
|
|
||
|
|
IBUFDS i_ibufds_sysref_1 (
|
||
|
|
.I (sysref_a_p),
|
||
|
|
.IB (sysref_a_n),
|
||
|
|
.O (sysref_a));
|
||
|
|
|
||
|
|
IBUFDS i_ibufds_sysref_2 (
|
||
|
|
.I (sysref_b_p),
|
||
|
|
.IB (sysref_b_n),
|
||
|
|
.O (sysref_b));
|
||
|
|
|
||
|
|
IBUFGDS i_rx_clk_ibufg_1 (
|
||
|
|
.I (core_clk_a_p),
|
||
|
|
.IB (core_clk_a_n),
|
||
|
|
.O (core_clk_a));
|
||
|
|
|
||
|
|
IBUFGDS i_rx_clk_ibufg_2 (
|
||
|
|
.I (core_clk_b_p),
|
||
|
|
.IB (core_clk_b_n),
|
||
|
|
.O (core_clk_b));
|
||
|
|
|
||
|
|
IBUFDS i_ibufds_tx_sync_1 (
|
||
|
|
.I (tx_sync_a_p),
|
||
|
|
.IB (tx_sync_a_n),
|
||
|
|
.O (tx_sync_a));
|
||
|
|
|
||
|
|
IBUFDS i_ibufds_tx_sync_2 (
|
||
|
|
.I (tx_sync_b_p),
|
||
|
|
.IB (tx_sync_b_n),
|
||
|
|
.O (tx_sync_b));
|
||
|
|
|
||
|
|
OBUFDS i_obufds_rx_sync_1 (
|
||
|
|
.I (rx_sync_rx),
|
||
|
|
.O (rx_sync_a_p),
|
||
|
|
.OB (rx_sync_a_n));
|
||
|
|
|
||
|
|
OBUFDS i_obufds_rx_os_sync_1 (
|
||
|
|
.I (rx_sync_obs),
|
||
|
|
.O (rx_os_sync_a_p),
|
||
|
|
.OB (rx_os_sync_a_n));
|
||
|
|
|
||
|
|
OBUFDS i_obufds_rx_sync_2 (
|
||
|
|
.I (rx_sync_rx),
|
||
|
|
.O (rx_sync_b_p),
|
||
|
|
.OB (rx_sync_b_n));
|
||
|
|
|
||
|
|
OBUFDS i_obufds_rx_os_sync_2 (
|
||
|
|
.I (rx_sync_obs),
|
||
|
|
.O (rx_os_sync_b_p),
|
||
|
|
.OB (rx_os_sync_b_n));
|
||
|
|
|
||
|
|
system_wrapper i_system_wrapper (
|
||
|
|
.gpio_i (gpio_i),
|
||
|
|
.gpio_o (gpio_o),
|
||
|
|
.gpio_t (gpio_t),
|
||
|
|
|
||
|
|
.ddr4_rtl_1_act_n(ddr4_rtl_1_act_n),
|
||
|
|
.ddr4_rtl_1_adr(ddr4_rtl_1_adr),
|
||
|
|
.ddr4_rtl_1_ba(ddr4_rtl_1_ba),
|
||
|
|
.ddr4_rtl_1_bg(ddr4_rtl_1_bg),
|
||
|
|
.ddr4_rtl_1_ck_c(ddr4_rtl_1_ck_c),
|
||
|
|
.ddr4_rtl_1_ck_t(ddr4_rtl_1_ck_t),
|
||
|
|
.ddr4_rtl_1_cke(ddr4_rtl_1_cke),
|
||
|
|
.ddr4_rtl_1_cs_n(ddr4_rtl_1_cs_n),
|
||
|
|
.ddr4_rtl_1_dm_n(ddr4_rtl_1_dm_n),
|
||
|
|
.ddr4_rtl_1_dq(ddr4_rtl_1_dq),
|
||
|
|
.ddr4_rtl_1_dqs_c(ddr4_rtl_1_dqs_c),
|
||
|
|
.ddr4_rtl_1_dqs_t(ddr4_rtl_1_dqs_t),
|
||
|
|
.ddr4_rtl_1_odt(ddr4_rtl_1_odt),
|
||
|
|
.ddr4_rtl_1_reset_n(ddr4_rtl_1_reset_n),
|
||
|
|
.sys_reset(1'b0),
|
||
|
|
.ddr4_ref_1_clk_n(ddr4_ref_1_clk_n),
|
||
|
|
.ddr4_ref_1_clk_p(ddr4_ref_1_clk_p),
|
||
|
|
.core_clk_a(core_clk_a),
|
||
|
|
.core_clk_b(core_clk_b),
|
||
|
|
.ref_clk_a(ref_clk_a),
|
||
|
|
.ref_clk_b(ref_clk_b),
|
||
|
|
.rx_data_0_n (rx_data_a_n[0]),
|
||
|
|
.rx_data_0_p (rx_data_a_p[0]),
|
||
|
|
.rx_data_1_n (rx_data_a_n[1]),
|
||
|
|
.rx_data_1_p (rx_data_a_p[1]),
|
||
|
|
.rx_data_2_n (rx_data_a_n[2]),
|
||
|
|
.rx_data_2_p (rx_data_a_p[2]),
|
||
|
|
.rx_data_3_n (rx_data_a_n[3]),
|
||
|
|
.rx_data_3_p (rx_data_a_p[3]),
|
||
|
|
.rx_data_4_n (rx_data_b_n[0]),
|
||
|
|
.rx_data_4_p (rx_data_b_p[0]),
|
||
|
|
.rx_data_5_n (rx_data_b_n[1]),
|
||
|
|
.rx_data_5_p (rx_data_b_p[1]),
|
||
|
|
.rx_data_6_n (rx_data_b_n[2]),
|
||
|
|
.rx_data_6_p (rx_data_b_p[2]),
|
||
|
|
.rx_data_7_n (rx_data_b_n[3]),
|
||
|
|
.rx_data_7_p (rx_data_b_p[3]),
|
||
|
|
.rx_sync_0 (rx_sync_rx),
|
||
|
|
.rx_sync_4 (rx_sync_obs),
|
||
|
|
.rx_sysref_0 (sysref_b),
|
||
|
|
.rx_sysref_4 (sysref_a),
|
||
|
|
.tx_data_0_n (tx_data_a_n[0]),
|
||
|
|
.tx_data_0_p (tx_data_a_p[0]),
|
||
|
|
.tx_data_1_n (tx_data_a_n[1]),
|
||
|
|
.tx_data_1_p (tx_data_a_p[1]),
|
||
|
|
.tx_data_2_n (tx_data_a_n[2]),
|
||
|
|
.tx_data_2_p (tx_data_a_p[2]),
|
||
|
|
.tx_data_3_n (tx_data_a_n[3]),
|
||
|
|
.tx_data_3_p (tx_data_a_p[3]),
|
||
|
|
.tx_data_4_n (tx_data_b_n[0]),
|
||
|
|
.tx_data_4_p (tx_data_b_p[0]),
|
||
|
|
.tx_data_5_n (tx_data_b_n[1]),
|
||
|
|
.tx_data_5_p (tx_data_b_p[1]),
|
||
|
|
.tx_data_6_n (tx_data_b_n[2]),
|
||
|
|
.tx_data_6_p (tx_data_b_p[2]),
|
||
|
|
.tx_data_7_n (tx_data_b_n[3]),
|
||
|
|
.tx_data_7_p (tx_data_b_p[3]),
|
||
|
|
.tx_sync_0 (tx_sync),
|
||
|
|
.tx_sysref_0 (sysref_a),
|
||
|
|
.dac_fifo_bypass(gpio_o[90]),
|
||
|
|
.spi0_csn(spi_csn),
|
||
|
|
.spi0_miso(spi0_miso),
|
||
|
|
.spi0_mosi(spi_mosi),
|
||
|
|
.spi0_sclk(spi_clk)
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
// ***************************************************************************
|
||
|
|
// ***************************************************************************
|