2019-09-24 15:43:15 +00:00
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# Instances and instance parameters
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set_instance_parameter_value sys_hps {CLK_EMACB_SOURCE} {1}
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set_instance_parameter_value sys_hps {CLK_EMAC_PTP_SOURCE} {1}
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2019-09-24 15:44:49 +00:00
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set_instance_parameter_value sys_hps {EMAC_PTP_REF_CLK} {100}
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2019-09-24 15:43:15 +00:00
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set_instance_parameter_value sys_hps {EMAC1_CLK} {250}
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2019-09-24 15:44:49 +00:00
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set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII_with_MDIO}
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2019-09-24 15:43:15 +00:00
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set_instance_parameter_value sys_hps {EMAC1_PTP} {0}
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set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {FPGA}
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set_instance_parameter_value sys_hps {EMAC1_SWITCH_Enable} {0}
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set_instance_parameter_value sys_hps {EMAC2_CLK} {250}
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2019-09-24 15:44:49 +00:00
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set_instance_parameter_value sys_hps {EMAC2_Mode} {RGMII_with_MDIO}
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2019-09-24 15:43:15 +00:00
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set_instance_parameter_value sys_hps {EMAC2_PTP} {0}
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2019-09-24 15:44:49 +00:00
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set_instance_parameter_value sys_hps {EMAC2_PinMuxing} {FPGA}
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2019-09-24 15:43:15 +00:00
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set_instance_parameter_value sys_hps {EMAC2_SWITCH_Enable} {0}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {125}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK} {125}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK} {2.5}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT} {100}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT} {100}
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# exported interfaces
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add_interface sys_hps_emac1 conduit end
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set_interface_property sys_hps_emac1 EXPORT_OF sys_hps.emac1
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add_interface sys_hps_emac1_md_clk clock source
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set_interface_property sys_hps_emac1_md_clk EXPORT_OF sys_hps.emac1_md_clk
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add_interface sys_hps_emac1_rx_clk_in clock sink
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set_interface_property sys_hps_emac1_rx_clk_in EXPORT_OF sys_hps.emac1_rx_clk_in
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add_interface sys_hps_emac1_tx_clk_in clock sink
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set_interface_property sys_hps_emac1_tx_clk_in EXPORT_OF sys_hps.emac1_tx_clk_in
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2019-09-24 15:44:49 +00:00
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add_interface sys_hps_emac2 conduit end
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set_interface_property sys_hps_emac2 EXPORT_OF sys_hps.emac2
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add_interface sys_hps_emac2_md_clk clock source
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set_interface_property sys_hps_emac2_md_clk EXPORT_OF sys_hps.emac2_md_clk
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add_interface sys_hps_emac2_rx_clk_in clock sink
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set_interface_property sys_hps_emac2_rx_clk_in EXPORT_OF sys_hps.emac2_rx_clk_in
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add_interface sys_hps_emac2_tx_clk_in clock sink
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set_interface_property sys_hps_emac2_tx_clk_in EXPORT_OF sys_hps.emac2_tx_clk_in
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2019-09-24 15:43:15 +00:00
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# internal connections
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add_connection sys_clk.clk sys_hps.emac_ptp_ref_clock
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