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pluto_hdl_adi/library/xilinx/util_adxcvr/util_adxcvr_constr.xdc

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util_adxcvr- rstdone on usrclk2
2016-07-13 19:23:02 +00:00
constraints: Update constraints Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.
2017-02-24 11:43:32 +00:00
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_rate*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *tx_rate*}]
util_adxcvr- rstdone on usrclk2
2016-07-13 19:23:02 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
util_adxcvr- add constraints file
2016-07-15 14:19:48 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
util_adxcvr- rstdone on usrclk2
2016-07-13 19:23:02 +00:00
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.
2020-12-18 14:43:28 +00:00
# sync bits i_sync_bits_tx_prbs_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_tx_prbs_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_prbs_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_rx_prbs_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_prbs_out
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_rx_prbs_out* && IS_SEQUENTIAL}]