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pluto_hdl_adi/projects/usdrx1/a5gt/system_constr.sdc

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usdrx1: Initial commit for a5gt axi_ad9671: added start of frame information to the altera core.
2014-10-07 16:41:54 +00:00
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00
create_clock -period "10.000 ns" -name sys_clk [get_ports {sys_clk}]
create_clock -period "12.500 ns" -name ref_clk [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name eth_rx_clk [get_ports {eth_rx_clk}]
usdrx1: Initial commit for a5gt axi_ad9671: added start of frame information to the altera core.
2014-10-07 16:41:54 +00:00
derive_pll_clocks
derive_clock_uncertainty
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00
set_clock_groups -exclusive \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 19:13:41 +00:00
set_false_path -to [get_registers *sysref_en_m1*]
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 19:13:41 +00:00
set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00
-to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 19:13:41 +00:00
set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
-through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 19:13:41 +00:00
set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00
-to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 19:13:41 +00:00
set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}]
usdrx1/a5gt- xcvr interface changes
2016-12-08 21:05:07 +00:00