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pluto_hdl_adi/library/axi_ad9152/Makefile

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makefile: added
2015-04-01 20:26:24 +00:00
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
## Copyright 2018(c) Analog Devices, Inc.
makefile: added
2015-04-01 20:26:24 +00:00
## Auto-generated, do not modify!
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
LIBRARY_NAME := axi_ad9152
makefile: added
2015-04-01 20:26:24 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += axi_ad9152.v
XILINX_DEPS += axi_ad9152_ip.tcl
axi_ad9152: Use the generic JESD204 DAC transmitter core Replace the axi_ad9152 implementation with the new generic JESD204 interface DAC core. The replacement is functionally equivalent. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:55:36 +00:00
XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
axi_ad9152: Use the generic JESD204 DAC transmitter core Replace the axi_ad9152 implementation with the new generic JESD204 interface DAC core. The replacement is functionally equivalent. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:55:36 +00:00
ALTERA_DEPS += ../common/ad_dds.v
ALTERA_DEPS += ../common/ad_dds_1.v
axi_ad9152: Updates for ad_dds phase acc wrapper
2018-06-06 11:17:24 +00:00
ALTERA_DEPS += ../common/ad_dds_2.v
ALTERA_DEPS += ../common/ad_dds_cordic_pipe.v
axi_ad9152: Use the generic JESD204 DAC transmitter core Replace the axi_ad9152 implementation with the new generic JESD204 interface DAC core. The replacement is functionally equivalent. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:55:36 +00:00
ALTERA_DEPS += ../common/ad_dds_sine.v
axi_ad9152: Updates for ad_dds phase acc wrapper
2018-06-06 11:17:24 +00:00
ALTERA_DEPS += ../common/ad_dds_sine_cordic.v
axi_ad9152: Use the generic JESD204 DAC transmitter core Replace the axi_ad9152 implementation with the new generic JESD204 interface DAC core. The replacement is functionally equivalent. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:55:36 +00:00
ALTERA_DEPS += ../common/ad_rst.v
ALTERA_DEPS += ../common/up_axi.v
ALTERA_DEPS += ../common/up_clock_mon.v
ALTERA_DEPS += ../common/up_dac_channel.v
ALTERA_DEPS += ../common/up_dac_common.v
ALTERA_DEPS += ../common/up_xfer_cntrl.v
ALTERA_DEPS += ../common/up_xfer_status.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
ALTERA_DEPS += axi_ad9152_hw.tcl
makefile: added
2015-04-01 20:26:24 +00:00
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
include ../scripts/library.mk