2017-03-20 16:15:18 +00:00
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# ad9361
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9361 axi_ad9361
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value axi_ad9361 {ID} {0}
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set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
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set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
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set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
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set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
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set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
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add_interface axi_ad9361_device_if conduit end
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set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
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add_interface axi_ad9361_up_enable conduit end
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set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
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add_interface axi_ad9361_up_txnrx conduit end
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set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
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add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
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add_connection sys_clk.clk axi_ad9361.if_delay_clk
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add_connection sys_clk.clk axi_ad9361.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
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# adc-wfifo & dac-rfifo
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2017-05-12 17:40:14 +00:00
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add_instance util_adc_wfifo util_wfifo
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
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set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
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set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
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set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
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add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
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add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
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2017-10-03 08:14:42 +00:00
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add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
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add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
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2017-03-20 16:15:18 +00:00
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add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
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add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
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add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
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add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
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add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
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# adc-wfifo & dac-rfifo
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2017-05-12 17:40:14 +00:00
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add_instance util_dac_rfifo util_rfifo
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
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set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
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set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
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set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
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add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
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add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
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2017-10-03 08:14:42 +00:00
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add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
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add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
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2017-03-20 16:15:18 +00:00
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add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
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add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
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add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
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add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
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add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
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# adc-pack & dac-unpack
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2018-10-05 08:08:37 +00:00
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add_instance util_adc_pack util_cpack2
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
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2018-10-05 08:08:37 +00:00
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set_instance_parameter_value util_adc_pack {SAMPLE_DATA_WIDTH} {16}
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add_connection sys_dma_clk.clk util_adc_pack.clk
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add_connection sys_dma_clk.clk_reset util_adc_pack.reset
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2017-03-20 16:15:18 +00:00
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add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
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add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
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add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
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add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
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2018-10-05 08:08:37 +00:00
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add_connection util_adc_pack.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
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2017-03-20 16:15:18 +00:00
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# adc-pack & dac-unpack
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2018-10-05 08:08:37 +00:00
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add_instance util_dac_upack util_upack2
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
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2018-10-05 08:08:37 +00:00
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set_instance_parameter_value util_dac_upack {SAMPLE_DATA_WIDTH} {16}
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add_connection sys_dma_clk.clk util_dac_upack.clk
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add_connection sys_dma_clk.clk_reset util_dac_upack.reset
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2017-03-20 16:15:18 +00:00
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add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
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add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
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add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
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add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
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2018-10-05 08:08:37 +00:00
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add_connection util_dac_upack.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
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2017-03-20 16:15:18 +00:00
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# adc-dma & dac-dma
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2017-05-12 17:40:14 +00:00
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add_instance axi_adc_dma axi_dmac
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value axi_adc_dma {ID} {0}
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set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
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2017-10-04 11:56:00 +00:00
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set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128}
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
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set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
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set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
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add_connection sys_clk.clk axi_adc_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
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add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
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2017-10-03 08:14:42 +00:00
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add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
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2018-10-05 08:08:37 +00:00
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add_connection util_adc_pack.if_packed_fifo_wr_en axi_adc_dma.if_fifo_wr_en
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add_connection util_adc_pack.if_packed_fifo_wr_sync axi_adc_dma.if_fifo_wr_sync
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add_connection util_adc_pack.if_packed_fifo_wr_data axi_adc_dma.if_fifo_wr_din
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add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_pack.if_packed_fifo_wr_overflow
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2017-03-20 16:15:18 +00:00
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# adc-dma & dac-dma
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2017-05-12 17:40:14 +00:00
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add_instance axi_dac_dma axi_dmac
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value axi_dac_dma {ID} {0}
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set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
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2018-10-05 08:08:37 +00:00
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set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {1}
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
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add_connection sys_clk.clk axi_dac_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
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add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
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2018-10-05 08:08:37 +00:00
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add_connection sys_dma_clk.clk axi_dac_dma.if_m_axis_aclk
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add_connection util_dac_upack.if_s_axis_valid axi_dac_dma.if_m_axis_valid
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add_connection util_dac_upack.if_s_axis_ready axi_dac_dma.if_m_axis_ready
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add_connection util_dac_upack.if_s_axis_data axi_dac_dma.if_m_axis_data
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2017-03-20 16:15:18 +00:00
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# interrupts
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ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender
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ad_cpu_interrupt 3 axi_dac_dma.interrupt_sender
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# cpu interconnects
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ad_cpu_interconnect 0x00120000 axi_ad9361.s_axi
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ad_cpu_interconnect 0x00100000 axi_adc_dma.s_axi
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ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
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# mem interconnects
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2017-10-04 11:56:00 +00:00
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set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 128 64}
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2017-03-20 16:15:18 +00:00
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2017-10-04 11:56:00 +00:00
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ad_dma_interconnect axi_adc_dma.m_dest_axi 1
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ad_dma_interconnect axi_dac_dma.m_src_axi 2
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2017-03-20 16:15:18 +00:00
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