80 lines
2.6 KiB
Coq
80 lines
2.6 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
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// clk_sel is 1. Provides a glitch free output clock
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// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
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module util_clkdiv #(
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parameter SIM_DEVICE = "CYCLONE5",
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parameter CLOCK_TYPE = "Global Clock") (
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input clk,
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input reset,
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output clk_out,
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output reset_out
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);
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reg enable;
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reg reset_d1;
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assign reset_out = reset | reset_d1;
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always @(posedge clk) begin
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reset_d1 <= reset;
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end
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always @(posedge clk) begin
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enable <= ~enable;
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end
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generate if (SIM_DEVICE == "CYCLONE5") begin
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cyclonev_clkena #(
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.clock_type ("Global Clock"),
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.ena_register_mode ("falling edge"),
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.lpm_type ("cyclonev_clkena")
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) clock_divider_by_2 (
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.ena(enable),
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.enaout(),
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.inclk(clk),
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// .clkselect (2'b0),
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.outclk(clk_out));
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end endgenerate
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endmodule // util_clkdiv
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