338 lines
10 KiB
Coq
338 lines
10 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_pwm_gen #(
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parameter ID = 0,
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parameter ASYNC_CLK_EN = 1,
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parameter N_PWMS = 1,
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parameter PWM_0_EXT_SYNC = 0,
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parameter EXT_ASYNC_SYNC = 0,
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parameter PULSE_0_WIDTH = 7,
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parameter PULSE_1_WIDTH = 7,
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parameter PULSE_2_WIDTH = 7,
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parameter PULSE_3_WIDTH = 7,
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parameter PULSE_0_PERIOD = 10,
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parameter PULSE_1_PERIOD = 10,
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parameter PULSE_2_PERIOD = 10,
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parameter PULSE_3_PERIOD = 10,
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parameter PULSE_1_OFFSET = 0,
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parameter PULSE_2_OFFSET = 0,
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parameter PULSE_3_OFFSET = 0)(
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input ext_clk,
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input ext_sync,
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output pwm_0,
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output pwm_1,
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output pwm_2,
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output pwm_3);
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// local parameters
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localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */
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8'h00, /* MINOR */
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8'h00}; /* PATCH */
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localparam [31:0] CORE_MAGIC = 32'h601a3471; // PLSG
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// internal registers
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reg sync_0;
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reg sync_1;
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reg sync_2;
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reg sync_3;
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reg sync_active_0;
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reg sync_active_1;
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reg sync_active_2;
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reg sync_active_3;
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// internal signals
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wire clk;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire up_wack_s;
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wire up_rack_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire [127:0] pwm_width_s;
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wire [127:0] pwm_period_s;
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wire [127:0] pwm_offset_s;
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wire [ 31:0] pwm_counter[0:N_PWMS-1];
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wire load_config_s;
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wire pwm_gen_resetn;
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wire ext_sync_s;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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axi_pwm_gen_regmap #(
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.ID (ID),
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.ASYNC_CLK_EN (ASYNC_CLK_EN),
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.CORE_MAGIC (CORE_MAGIC),
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.CORE_VERSION (CORE_VERSION),
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.N_PWMS (N_PWMS),
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.PULSE_0_WIDTH (PULSE_0_WIDTH),
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.PULSE_1_WIDTH (PULSE_1_WIDTH),
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.PULSE_2_WIDTH (PULSE_2_WIDTH),
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.PULSE_3_WIDTH (PULSE_3_WIDTH),
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.PULSE_0_PERIOD (PULSE_0_PERIOD),
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.PULSE_1_PERIOD (PULSE_1_PERIOD),
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.PULSE_2_PERIOD (PULSE_2_PERIOD),
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.PULSE_3_PERIOD (PULSE_3_PERIOD),
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.PULSE_1_OFFSET (PULSE_1_OFFSET),
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.PULSE_2_OFFSET (PULSE_2_OFFSET),
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.PULSE_3_OFFSET (PULSE_3_OFFSET))
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i_regmap (
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.ext_clk (ext_clk),
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.clk_out (clk),
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.pwm_gen_resetn (pwm_gen_resetn),
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.pwm_width (pwm_width_s),
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.pwm_period (pwm_period_s),
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.pwm_offset (pwm_offset_s),
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.load_config (load_config_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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axi_pwm_gen_1 #(
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.PULSE_WIDTH (PULSE_0_WIDTH),
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.PULSE_PERIOD (PULSE_0_PERIOD))
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i0_axi_pwm_gen_1(
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.clk (clk),
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.rstn (pwm_gen_resetn),
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.pulse_width (pwm_width_s[31:0]),
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.pulse_period (pwm_period_s[31:0]),
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.load_config (load_config_s),
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.sync (sync_0),
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.pulse (pwm_0),
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.pulse_counter (pwm_counter[0]));
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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sync_active_0 <= 1'b1;
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sync_0 <= 1'b1;
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end else begin
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sync_active_0 <= PWM_0_EXT_SYNC;
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if (sync_active_0) begin
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sync_0 <= ext_sync_s;
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end else begin
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sync_0 <= 1'b0;
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end
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end
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end
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generate
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reg ext_sync_m0 = 1'b1;
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reg ext_sync_m1 = 1'b1;
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if (EXT_ASYNC_SYNC) begin
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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ext_sync_m0 <= 1'b1;
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ext_sync_m1 <= 1'b1;
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end else begin
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ext_sync_m0 <= ext_sync;
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ext_sync_m1 <= ext_sync_m0;
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end
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end
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assign ext_sync_s = ext_sync_m1;
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end else begin
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assign ext_sync_s = ext_sync;
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end
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if (N_PWMS >= 2) begin
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axi_pwm_gen_1 #(
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.PULSE_WIDTH (PULSE_1_WIDTH),
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.PULSE_PERIOD (PULSE_1_PERIOD))
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i1_axi_pwm_gen_1(
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.clk (clk),
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.rstn (pwm_gen_resetn),
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.pulse_width (pwm_width_s[63:32]),
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.pulse_period (pwm_period_s[63:32]),
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.load_config (load_config_s),
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.sync (sync_1),
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.pulse (pwm_1),
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.pulse_counter (pwm_counter[1]));
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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sync_active_1 <= 1'b1;
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sync_1 <= 1'b1;
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end else begin
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sync_active_1 <= |pwm_offset_s[63:32];
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if (sync_active_1) begin
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sync_1 <= (pwm_counter[0] == pwm_offset_s[63:32]) ? 1'b0 : 1'b1;
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end else begin
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sync_1 <= 1'b0;
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end
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end
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end
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end else begin
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assign pwm_1 = 1'b0;
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end
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if (N_PWMS >= 3) begin
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axi_pwm_gen_1 #(
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.PULSE_WIDTH (PULSE_2_WIDTH),
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.PULSE_PERIOD (PULSE_2_PERIOD))
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i2_axi_pwm_gen_1(
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.clk (clk),
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.rstn (pwm_gen_resetn),
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.pulse_width (pwm_width_s[95:64]),
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.pulse_period (pwm_period_s[95:64]),
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.load_config (load_config_s),
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.sync (sync_2),
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.pulse (pwm_2),
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.pulse_counter (pwm_counter[2]));
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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sync_active_2 <= 1'b1;
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sync_2 <= 1'b1;
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end else begin
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sync_active_2 <= |pwm_offset_s[95:64];
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if (sync_active_2) begin
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sync_2 <= (pwm_counter[0] == pwm_offset_s[95:64]) ? 1'b0 : 1'b1;
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end else begin
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sync_2 <= 1'b0;
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end
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end
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end
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end else begin
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assign pwm_2 = 1'b0;
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end
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if (N_PWMS >= 4) begin
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axi_pwm_gen_1 #(
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.PULSE_WIDTH (PULSE_3_WIDTH),
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.PULSE_PERIOD (PULSE_3_PERIOD))
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i3_axi_pwm_gen_1(
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.clk (clk),
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.rstn (pwm_gen_resetn),
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.pulse_width (pwm_width_s[127:96]),
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.pulse_period (pwm_period_s[127:96]),
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.load_config (load_config_s),
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.sync (sync_3),
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.pulse (pwm_3),
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.pulse_counter (pwm_counter[3]));
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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sync_active_3 <= 1'b1;
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sync_3 <= 1'b1;
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end else begin
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sync_active_3 <= |pwm_offset_s[127:96];
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if (sync_active_3) begin
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sync_3 <= (pwm_counter[0] == pwm_offset_s[127:96]) ? 1'b0 : 1'b1;
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end else begin
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sync_3 <= 1'b0;
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end
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end
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end
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end else begin
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assign pwm_3 = 1'b0;
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end
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endgenerate
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up_axi #(
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.AXI_ADDRESS_WIDTH(16))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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endmodule
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