zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl

217 lines
7.9 KiB
Tcl
Raw Normal View History

Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact jesd204-licensing@analog.com for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
global VIVADO_IP_LIBRARY
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
adi_ip_create jesd204_tx
adi_ip_files jesd204_tx [list \
jesd204: Fix file names All the file names must have the same name as its module. Change all the files, which did not respect this rule. Update all the make files and Tcl scripts.
2018-03-28 13:44:06 +00:00
"jesd204_tx_lane.v" \
jesd204_tx: Support for 64b mode in transmit peripheral Instantiate 64B/66B mode encoder based on synthesis parameter.
2019-10-01 15:12:11 +00:00
"jesd204_tx_lane_64b.v" \
"jesd204_tx_header.v" \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
"jesd204_tx_gearbox.v" \
jesd204: Fix file names All the file names must have the same name as its module. Change all the files, which did not respect this rule. Update all the make files and Tcl scripts.
2018-03-28 13:44:06 +00:00
"jesd204_tx_ctrl.v" \
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
"jesd204_tx_constr.ttcl" \
jesd204: Add out of context constraint file for link layer cores For the out of context flow it is important to have all clocks defined at the interface, especially if the clock are used in the other constraints.
2021-04-21 12:53:45 +00:00
"jesd204_tx_ooc.ttcl" \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
"../../common/ad_upack.v" \
"jesd204_tx.v" \
"bd/bd.tcl"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
]
adi_ip_properties_lite jesd204_tx
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
jesd204: Add out of context constraint file for link layer cores For the out of context flow it is important to have all clocks defined at the interface, especially if the clock are used in the other constraints.
2021-04-21 12:53:45 +00:00
adi_ip_ttcl jesd204_tx "jesd204_tx_ooc.ttcl"
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
adi_ip_bd jesd204_tx "bd/bd.tcl"
jesd204- apply constraints after top
2017-06-16 19:30:18 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:jesd204_common:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
set_property display_name "ADI JESD204 Transmit" [ipx::current_core]
set_property description "ADI JESD204 Transmit" [ipx::current_core]
adi_add_bus "tx_data" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
jesd204: jesd204_tx: Add dummy valid for the TX data interface The Xilinx tools are quite forgiving when it comes to required signals on standard interfaces, which is why it was possible to define a AXI streaming interface without the required valid signal. The Altera tools are more strict and wont allow this. Add a dummy valid signal to the TX data interface to make the tools happy. For now the signal does not do anything, in the future it might be used to detect an underflow condition on the data interface and report this through the status interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 13:32:16 +00:00
{ "tx_valid" "TVALID" } \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
{ "tx_ready" "TREADY" } \
{ "tx_data" "TDATA" } \
}
jesd204: support for 16 lanes
2019-10-31 11:16:25 +00:00
adi_add_multi_bus 16 "tx_phy" "master" \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
"xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
"xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
[list \
jesd204_tx: Support for 64b mode in transmit peripheral Instantiate 64B/66B mode encoder based on synthesis parameter.
2019-10-01 15:12:11 +00:00
{ "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
{ "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
{ "phy_header" "txheader" 2} \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
] \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
adi_add_bus "tx_cfg" "slave" \
"analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
"analog.com:interface:jesd204_tx_cfg:1.0" \
{ \
{ "cfg_lanes_disable" "lanes_disable" } \
jesd204_tx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a TX link this means that the FPGA receives multiple SYNC signals, one for each link. The state machine of the TX link peripheral must combine those SYNC signals into a single SYNC signal that is asserted when either of the external SYNC signals is asserted. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the use case profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the TX FSM.
2018-03-29 09:38:34 +00:00
{ "cfg_links_disable" "links_disable" } \
jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode, and frame alignment character replace/insert with or without scrambling. Add support for xcelium simulator to jesd204/tb Increased cores minor version.
2020-01-30 22:05:13 +00:00
{ "cfg_octets_per_multiframe" "octets_per_multiframe" } \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
{ "cfg_octets_per_frame" "octets_per_frame" } \
{ "cfg_continuous_cgs" "continuous_cgs" } \
{ "cfg_continuous_ilas" "continuous_ilas" } \
{ "cfg_skip_ilas" "skip_ilas" } \
{ "cfg_mframes_per_ilas" "mframes_per_ilas" } \
{ "cfg_disable_char_replacement" "disable_char_replacement" } \
{ "cfg_disable_scrambler" "disable_scrambler" } \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
{ "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \
{ "device_cfg_octets_per_frame" "device_octets_per_frame" } \
{ "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \
{ "device_cfg_lmfc_offset" "device_lmfc_offset" } \
{ "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \
{ "device_cfg_sysref_disable" "device_sysref_disable" } \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
}
adi_add_bus "tx_ilas_config" "master" \
"analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
"analog.com:interface:jesd204_tx_ilas_config:1.0" \
{ \
{ "ilas_config_rd" "rd" } \
{ "ilas_config_addr" "addr" } \
{ "ilas_config_data" "data" } \
}
adi_add_bus "tx_event" "master" \
"analog.com:interface:jesd204_tx_event_rtl:1.0" \
"analog.com:interface:jesd204_tx_event:1.0" \
{ \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
{ "device_event_sysref_alignment_error" "sysref_alignment_error" } \
{ "device_event_sysref_edge" "sysref_edge" } \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
}
adi_add_bus "tx_status" "master" \
"analog.com:interface:jesd204_tx_status_rtl:1.0" \
"analog.com:interface:jesd204_tx_status:1.0" \
{ \
{ "status_state" "state" } \
{ "status_sync" "sync" } \
jesd204: Expose core synthesis parameters through registers Make synthesis parameters accessible for the drivers. Rework implementation to reflect the parameters of the actual core and not of the AXI interfacing core.
2020-12-03 13:59:33 +00:00
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
}
adi_add_bus "tx_ctrl" "slave" \
"analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
"analog.com:interface:jesd204_tx_ctrl:1.0" \
{ \
{ "ctrl_manual_sync_request" "manual_sync_request" } \
}
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
adi_add_bus_clock "clk" "tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" "reset"
adi_add_bus_clock "device_clk" "tx_data" "device_reset"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
jesd204_tx: Support for 64b mode in transmit peripheral Instantiate 64B/66B mode encoder based on synthesis parameter.
2019-10-01 15:12:11 +00:00
adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_ports_dependency "sync" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
jesd204_tx: Support for 64b mode in transmit peripheral Instantiate 64B/66B mode encoder based on synthesis parameter.
2019-10-01 15:12:11 +00:00
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
# Data width selection
set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
set_property -dict [list \
jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode, and frame alignment character replace/insert with or without scrambling. Add support for xcelium simulator to jesd204/tb Increased cores minor version.
2020-01-30 22:05:13 +00:00
enablement_tcl_expr {$LINK_MODE==1} \
jesd204_tx: Support for 64b mode in transmit peripheral Instantiate 64B/66B mode encoder based on synthesis parameter.
2019-10-01 15:12:11 +00:00
value_tcl_expr {expr $LINK_MODE*4} \
] $param
# SYSREF IOB placement
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
set param [ipx::add_user_parameter SYSREF_IOB $cc]
set_property -dict {value_resolve_type user value_format bool value true} $param
set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
set_property -dict [list \
display_name {Place SYSREF in IOB} \
widget {checkBox} \
show_label true \
] $param
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
-parent $page0 -display_name {Clock Domain Configuration}]
set p [ipgui::get_guiparamspec -name "ASYNC_CLK" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $clk_group
set_property -dict [list \
"display_name" "Link and Device Clock Asynchronous" \
"widget" "checkBox" \
] $p
jesd204_rx/tx: make SYSREF IOB placement optional In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation.
2018-07-23 11:58:46 +00:00
ipx::create_xgui_files [ipx::current_core]
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ipx::save_core [ipx::current_core]