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pluto_hdl_adi/library/axi_ad9144/axi_ad9144_ip.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# ip
source ../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
global VIVADO_IP_LIBRARY
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
"axi_ad9144.v" ]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
adi_ip_properties axi_ad9144
library: Update scripts/adi_ad_ip.tcl and IPs Fix library makefiles dep list using generic vendor info reg Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure. This change will simplify the process of generating makefiles for each library. Removing the bd.tcl script from the adi_ip_files list will remove it from the make dependency list.
2019-04-02 08:18:25 +00:00
adi_init_bd_tcl
library/IPs: Auto-generate bd.tcl Update Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to auto-generate bd.tcl for: - axi_ad5766/axi_ad5766_ip.tcl - axi_ad6676/axi_ad6676_ip.tcl - axi_ad9122/axi_ad9122_ip.tcl - axi_ad9144/axi_ad9144_ip.tcl - axi_ad9152/axi_ad9152_ip.tcl - axi_ad9162/axi_ad9162_ip.tcl - axi_ad9250/axi_ad9250_ip.tcl - axi_ad9265/axi_ad9265_ip.tcl - axi_ad9361/axi_ad9361_ip.tcl - axi_ad9371/axi_ad9371_ip.tcl - axi_ad9434/axi_ad9434_ip.tcl - axi_ad9467/axi_ad9467_ip.tcl - axi_ad9625/axi_ad9625_ip.tcl - axi_ad9671/axi_ad9671_ip.tcl - axi_ad9680/axi_ad9680_ip.tcl - axi_ad9684/axi_ad9684_ip.tcl - axi_ad9739a/axi_ad9739a_ip.tcl - axi_ad9963/axi_ad9963_ip.tcl - axi_adrv9009/axi_adrv9009_ip.tcl - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl - axi_hdmi_tx/axi_hdmi_tx_ip.tcl - xilinx/axi_adxcvr/Makefile - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl - xilinx/util_adxcvr/Makefile - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-14 15:25:36 +00:00
adi_ip_bd axi_ad9144 "bd/bd.tcl"
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
library: Add link to wiki for IPs
2021-10-20 15:08:35 +00:00
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9144} [ipx::current_core]
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_dac:1.0 \
]
axi_ad9144: Use the generic JESD204 DAC transmitter core Replace the axi_ad9144 implementation with the new generic JESD204 interface DAC core. The replacement is functionally equivalent. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 16:55:22 +00:00
axi_ad9144: Hide unused ports in DUAL mode In DUAL mode half of the data ports are unused and the unused inputs need to be connected to dummy signals. Completely hide the unused ports in DUAL mode to remove that requirement. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-07 18:41:43 +00:00
adi_set_ports_dependency "dac_valid_2" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_valid_3" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_enable_2" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_enable_3" "QUAD_OR_DUAL_N == 1"
adi_set_ports_dependency "dac_ddata_2" "QUAD_OR_DUAL_N == 1" "0"
adi_set_ports_dependency "dac_ddata_3" "QUAD_OR_DUAL_N == 1" "0"
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
axi_ad9144- qsys updates
2016-09-12 18:55:02 +00:00
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
axi_ad9144: Infer clock signal
2018-04-05 12:47:58 +00:00
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ipx::save_core [ipx::current_core]