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pluto_hdl_adi/projects/fmcjesdadc1/vc707/system_bd.tcl

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fmcjesdadc1: Initial commit of VC707 version
2014-09-01 15:47:01 +00:00
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source ../common/fmcjesdadc1_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 15:47:01 +00:00
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
fmcjesdadc1: Update block design (#743) Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-09-08 14:19:57 +00:00
ad_ip_parameter axi_ad9250_dma CONFIG.DMA_DATA_WIDTH_DEST 256
ad_ip_parameter axi_ad9250_dma CONFIG.FIFO_SIZE 32