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pluto_hdl_adi/projects/daq3/vcu118/system_project.tcl

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daq3: vcu118 initial commit
2019-03-06 07:34:05 +00:00
source ../../scripts/adi_env.tcl
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2018-08-14 08:43:32 +00:00
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
daq3: vcu118 initial commit
2019-03-06 07:34:05 +00:00
source $ad_hdl_dir/projects/scripts/adi_board.tcl
daq3: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-26 11:34:14 +00:00
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
# Parameter description:
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_S : Number of samples per frame
adi_project daq3_vcu118 0 [list \
RX_JESD_M [get_env_param RX_JESD_M 2 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 2 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
]
daq3: vcu118 initial commit
2019-03-06 07:34:05 +00:00
adi_project_files daq3_vcu118 [list \
"../common/daq3_spi.v" \
"system_top.v" \
"system_constr.xdc"\
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
"$ad_hdl_dir/library/common/ad_iobuf.v" \
daq3: vcu118 initial commit
2019-03-06 07:34:05 +00:00
"$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
## To improve timing in DDR4 MIG
set_property strategy Performance_Retiming [get_runs impl_1]
adi_project_run daq3_vcu118