2015-12-10 14:41:37 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2017-10-25 13:41:26 +00:00
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create_clock -period "1.621 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
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create_clock -period "1.621 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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2015-12-10 14:41:37 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2017-06-07 14:22:08 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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2016-05-27 12:37:26 +00:00
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2017-10-06 07:45:33 +00:00
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# flash interface
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set_false_path -from * -to [get_ports {flash_resetn}]
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