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pluto_hdl_adi/projects/adrv9364z7020/ccbob_cmos/system_bd.tcl

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Tcl
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pzsdr1- cmos mode
2016-04-11 19:58:29 +00:00
adrv9364z7020: Rename pzsdr1 to adrv9364z7020
2017-05-25 14:20:23 +00:00
source ../common/adrv9364z7020_bd.tcl
source ../common/ccbob_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
pzsdr1- cmos mode
2016-04-11 19:58:29 +00:00
ad9361- clkdiv to util_ad9361_divclk
2017-08-07 15:25:46 +00:00
ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2
ad_ip_parameter util_ad9361_divclk CONFIG.SEL_1_DIV 1
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 10:01:24 +00:00
pzsdr1/ccbrk_cmos- updates
2016-11-17 20:32:49 +00:00
cfg_ad9361_interface CMOS
pzsdr1- cmos mode
2016-04-11 19:58:29 +00:00
ad9361- delay initialization
2017-03-15 16:06:49 +00:00
set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361]
adrv9364: Added sysid to all projects
2019-11-18 11:03:07 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file