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pluto_hdl_adi/projects/ad9656_fmc/zcu102/system_project.tcl

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ad9656:Add reference design for the ad9656 eval board (#494) Added reference design for the ad9656 evaluation board coupled with the zcu102 carrier board. The JESD204 communication link that transfers data from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1, F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2020-10-06 06:53:40 +00:00
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9656_fmc_zcu102
adi_project_files ad9656_fmc_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run ad9656_fmc_zcu102