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pluto_hdl_adi/library/xilinx/common/ad_mmcm_drp.v

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
ad_mmcm_drp: Fix generate block Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate.
2017-04-20 15:43:37 +00:00
//
license: Add some clarification to the header license
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
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// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
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//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
ad_mmcm_drp: Fix generate block Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate.
2017-04-20 15:43:37 +00:00
//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
ad_mmcm_drp: Fix generate block Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate.
2017-04-20 15:43:37 +00:00
//
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
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// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// OR
//
license: Add some clarification to the header license
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// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
//
// ***************************************************************************
// ***************************************************************************
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
// MMCM_OR_BUFR_N with DRP and device specific
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
`timescale 1ns/100ps
all: Update verilog files to verilog-2001
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module ad_mmcm_drp #(
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
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parameter FPGA_TECHNOLOGY = 0,
all: Update verilog files to verilog-2001
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parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_CLKIN2_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK0_PHASE = 0.000,
parameter MMCM_CLK1_DIV = 6,
parameter MMCM_CLK1_PHASE = 0.000,
parameter MMCM_CLK2_DIV = 2.000,
parameter MMCM_CLK2_PHASE = 0.000) (
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
// clocks
all: Update verilog files to verilog-2001
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input clk,
input clk2,
input clk_sel,
input mmcm_rst,
output mmcm_clk_0,
output mmcm_clk_1,
output mmcm_clk_2,
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
// drp interface
all: Update verilog files to verilog-2001
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input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [15:0] up_drp_wdata,
output reg [15:0] up_drp_rdata,
output reg up_drp_ready,
output reg up_drp_locked);
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
localparam SEVEN_SERIES = 1;
localparam ULTRASCALE = 2;
localparam ULTRASCALE_PLUS = 3;
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
// internal registers
reg up_drp_locked_m1 = 'd0;
// internal signals
wire bufg_fb_clk_s;
wire mmcm_fb_clk_s;
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
common/mmcm: add another clock
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wire mmcm_clk_2_s;
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
wire mmcm_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
common/up_* : Make up_rstn synchronous to up_clk The up_rstn is driven by s_axi_resetn, which is generated by a Processor System Reset module. (connected to port peripheral_aresetn) Therefor using this reset signal as an asynchronous reset is redundant, and a bad design practice at the same time. Asynchronous reset should be used if it's inevitable.
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always @(posedge up_clk) begin
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
// instantiations
generate
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
ad_mmcm_drp: Fix generate block Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate.
2017-04-20 15:43:37 +00:00
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
end else if (FPGA_TECHNOLOGY == ULTRASCALE) begin
axi_clkgen: add ultrascale series support
2018-01-29 08:33:12 +00:00
MMCME3_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("AUTO"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcme3 (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.CDDCREQ (1'b0),
.CDDCDONE (),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
end else if (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
MMCME4_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("AUTO"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD)
) i_mmcme4 (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
axi_clkgen: add ultrascale series support
2018-01-29 08:33:12 +00:00
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.CDDCREQ (1'b0),
.CDDCDONE (),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************