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pluto_hdl_adi/library/xilinx/util_adxcvr/util_adxcvr_xcm.v

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util_adxcvr- added
2016-06-14 16:18:56 +00:00
// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
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// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
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//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// OR
//
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
util_adxcvr- added
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
util_adxcvr- xcvr_type parameter
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module util_adxcvr_xcm #(
// parameters
parameter integer XCVR_TYPE = 0,
util_adxcvr- parameter defaults
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parameter integer QPLL_REFCLK_DIV = 1,
util_adxcvr- xcvr_type parameter
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parameter integer QPLL_FBDIV_RATIO = 1,
util_adxcvr: Add GTH parameters for line rate of 15Gbps
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parameter [15:0] POR_CFG = 16'b0000000000000110,
parameter [15:0] PPF0_CFG = 16'b0000011000000000,
util_adxcvr- parameter defaults
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parameter [26:0] QPLL_CFG = 27'h0680181,
util_adxcvr: Expose QPLL and CPLL *_CFG attributes
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parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,
parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,
parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,
util_adxcvr: Expose GTY4 parameters required for 15Gbps link These parameters must be overwritten when the link is at 15Gbps. The parameters have a GTY4_ prefix since the same parameters are shared between GTY4 and GTH4 having different default values.
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parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,
util_adxcvr: Add GTH parameters for line rate of 15Gbps
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parameter [15:0] QPLL_CP_G3 = 10'b0000011111,
parameter [15:0] QPLL_LPF = 10'b0100110111,
parameter [15:0] QPLL_CP = 10'b0001111111,
util_adxcvr: Expose GTY4 parameters required for 15Gbps link These parameters must be overwritten when the link is at 15Gbps. The parameters have a GTY4_ prefix since the same parameters are shared between GTY4 and GTH4 having different default values.
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parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000
util_adxcvr: Add GTH parameters for line rate of 15Gbps
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util_adxcvr: Expose GTY4 parameters required for 15Gbps link These parameters must be overwritten when the link is at 15Gbps. The parameters have a GTY4_ prefix since the same parameters are shared between GTY4 and GTH4 having different default values.
2019-04-15 07:59:06 +00:00
) (
util_adxcvr- added
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// reset and clocks
util_adxcvr: shared xcvr cores
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input qpll_ref_clk,
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
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input qpll_sel,
util_adxcvr: shared xcvr cores
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output qpll2ch_clk,
output qpll2ch_ref_clk,
output qpll2ch_locked,
axi/util_adxcvr: Add GTYE4 transceiver support
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util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
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output qpll1_clk,
output qpll1_ref_clk,
output qpll1_locked,
util_adxcvr- added
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// drp interface
util_adxcvr: shared xcvr cores
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input up_rstn,
util_adxcvr- added
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input up_clk,
util_adxcvr: shared xcvr cores
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input up_qpll_rst,
input up_cm_enb,
input [11:0] up_cm_addr,
input up_cm_wr,
input [15:0] up_cm_wdata,
output [15:0] up_cm_rdata,
output up_cm_ready);
util_adxcvr- added
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Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
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localparam GTXE2_TRANSCEIVERS = 2;
localparam GTHE3_TRANSCEIVERS = 5;
localparam GTHE4_TRANSCEIVERS = 8;
axi/util_adxcvr: Add GTYE4 transceiver support
2019-02-11 17:15:51 +00:00
localparam GTYE4_TRANSCEIVERS = 9;
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
util_adxcvr: shared xcvr cores
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// internal registers
util_adxcvr- added
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util_adxcvr: shared xcvr cores
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reg up_enb_int = 'd0;
reg [11:0] up_addr_int = 'd0;
reg up_wr_int = 'd0;
reg [15:0] up_wdata_int = 'd0;
reg [15:0] up_rdata_int = 'd0;
reg up_ready_int = 'd0;
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
reg up_sel_int = 'd0;
util_adxcvr: shared xcvr cores
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// internal signals
wire [15:0] up_rdata_s;
wire up_ready_s;
// drp access
assign up_cm_rdata = up_rdata_int;
assign up_cm_ready = up_ready_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 16'd0;
up_rdata_int <= 16'd0;
up_ready_int <= 1'd0;
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
up_sel_int <= 1'b0;
util_adxcvr: shared xcvr cores
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end else begin
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
if (up_cm_enb == 1'b1) begin
util_adxcvr: shared xcvr cores
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up_enb_int <= up_cm_enb;
up_addr_int <= up_cm_addr;
up_wr_int <= up_cm_wr;
up_wdata_int <= up_cm_wdata;
end else begin
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 16'd0;
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
end
if (up_cm_enb == 1'b1) begin
up_sel_int <= 1'b1;
end else if (up_ready_s == 1'b1) begin
up_sel_int <= 1'b0;
end
if (up_sel_int == 1'b1) begin
up_ready_int <= up_ready_s;
up_rdata_int <= up_rdata_s;
end else begin
up_ready_int <= 1'b0;
up_rdata_int <= 'h00;
util_adxcvr: shared xcvr cores
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end
end
util_adxcvr- added
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end
util_adxcvr: shared xcvr cores
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// instantiations
util_adxcvr- added
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generate
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
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assign qpll1_locked = 1'b0;
assign qpll1_clk = 1'b0;
assign qpll1_ref_clk = 1'b0;
util_adxcvr- added
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GTXE2_COMMON #(
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
util_adxcvr- parameter defaults
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.IS_DRPCLK_INVERTED (1'b0),
.IS_GTGREFCLK_INVERTED (1'b0),
.IS_QPLLLOCKDETCLK_INVERTED (1'b0),
util_adxcvr- added
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.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
util_adxcvr- parameter defaults
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.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION ("4.0"))
util_adxcvr- added
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i_gtxe2_common (
Fix warnings
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.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.REFCLKOUTMONITOR (),
util_adxcvr- parameter defaults
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.BGBYPASSB (1'h1),
.BGMONITORENB (1'h1),
.BGPDB (1'h1),
.BGRCALOVRD (5'h1f),
util_adxcvr: shared xcvr cores
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.DRPADDR (up_addr_int[7:0]),
util_adxcvr- parameter defaults
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.DRPCLK (up_clk),
util_adxcvr: shared xcvr cores
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.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
util_adxcvr- parameter defaults
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.DRPEN (up_enb_int),
util_adxcvr: shared xcvr cores
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.DRPRDY (up_ready_s),
util_adxcvr- parameter defaults
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.DRPWE (up_wr_int),
.GTGREFCLK (1'h0),
.GTNORTHREFCLK0 (1'h0),
.GTNORTHREFCLK1 (1'h0),
util_adxcvr: shared xcvr cores
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.GTREFCLK0 (qpll_ref_clk),
util_adxcvr- parameter defaults
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.GTREFCLK1 (1'h0),
.GTSOUTHREFCLK0 (1'h0),
.GTSOUTHREFCLK1 (1'h0),
.PMARSVD (8'h0),
util_adxcvr: shared xcvr cores
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.QPLLLOCK (qpll2ch_locked),
util_adxcvr- added
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.QPLLLOCKDETCLK (up_clk),
util_adxcvr- parameter defaults
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.QPLLLOCKEN (1'h1),
.QPLLOUTCLK (qpll2ch_clk),
.QPLLOUTREFCLK (qpll2ch_ref_clk),
.QPLLOUTRESET (1'h0),
.QPLLPD (1'h0),
util_adxcvr- added
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.QPLLREFCLKLOST (),
util_adxcvr- parameter defaults
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.QPLLREFCLKSEL (3'h1),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.QPLLRESET (up_qpll_rst),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.QPLLRSVD1 (16'h0),
.QPLLRSVD2 (5'h1f),
.RCALENB (1'h1));
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end
endgenerate
generate
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin
util_adxcvr- added
2016-06-14 16:18:56 +00:00
GTHE3_COMMON #(
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.BIAS_CFG0 (16'h0000),
.BIAS_CFG1 (16'h0000),
.BIAS_CFG2 (16'h0000),
.BIAS_CFG3 (16'h0040),
.BIAS_CFG4 (16'h0000),
.BIAS_CFG_RSVD (10'b0000000000),
.COMMON_CFG0 (16'h0000),
.COMMON_CFG1 (16'h0000),
.POR_CFG (16'h0004),
.QPLL0_CFG0 (16'h321c),
.QPLL0_CFG1 (16'h1018),
.QPLL0_CFG1_G3 (16'h1018),
.QPLL0_CFG2 (16'h0048),
.QPLL0_CFG2_G3 (16'h0048),
.QPLL0_CFG3 (16'h0120),
.QPLL0_CFG4 (16'h0000),
.QPLL0_CP (10'b0000011111),
.QPLL0_CP_G3 (10'b1111111111),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (80),
.QPLL0_INIT_CFG0 (16'h02b2),
.QPLL0_INIT_CFG1 (8'h00),
.QPLL0_LOCK_CFG (16'h21e8),
.QPLL0_LOCK_CFG_G3 (16'h21e8),
.QPLL0_LPF (10'b1111111111),
.QPLL0_LPF_G3 (10'b0000010101),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.QPLL0_SDM_CFG0 (16'b0000000000000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLL1_CFG0 (16'h321c),
.QPLL1_CFG1 (16'h1018),
.QPLL1_CFG1_G3 (16'h1018),
.QPLL1_CFG2 (16'h0040),
.QPLL1_CFG2_G3 (16'h0040),
.QPLL1_CFG3 (16'h0120),
.QPLL1_CFG4 (16'h0000),
.QPLL1_CP (10'b0000011111),
.QPLL1_CP_G3 (10'b1111111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'h02b2),
.QPLL1_INIT_CFG1 (8'h00),
.QPLL1_LOCK_CFG (16'h21e8),
.QPLL1_LOCK_CFG_G3 (16'h21e8),
.QPLL1_LPF (10'b1111111111),
.QPLL1_LPF_G3 (10'b0000010101),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.QPLL1_SDM_CFG0 (16'b0000000000000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RSVD_ATTR0 (16'h0000),
.RSVD_ATTR1 (16'h0000),
.RSVD_ATTR2 (16'h0000),
.RSVD_ATTR3 (16'h0000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SARC_EN (1'b1),
.SARC_SEL (1'b0),
.SDM0DATA1_0 (16'b0000000000000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SDM0DATA1_1 (9'b000000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SDM0INITSEED0_0 (16'b0000000000000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SDM0INITSEED0_1 (9'b000000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SDM0_DATA_PIN_SEL (1'b0),
.SDM0_WIDTH_PIN_SEL (1'b0),
.SDM1DATA1_0 (16'b0000000000000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SDM1DATA1_1 (9'b000000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SDM1INITSEED0_0 (16'b0000000000000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SDM1INITSEED0_1 (9'b000000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SDM1_DATA_PIN_SEL (1'b0),
.SDM1_WIDTH_PIN_SEL (1'b0),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION (2))
util_adxcvr- added
2016-06-14 16:18:56 +00:00
i_gthe3_common (
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.BGBYPASSB (1'h1),
.BGMONITORENB (1'h1),
.BGPDB (1'h1),
.BGRCALOVRD (5'h1f),
.BGRCALOVRDENB (1'h1),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPADDR (up_addr_int[8:0]),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.DRPCLK (up_clk),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPDI (up_wdata_int),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.DRPDO (up_rdata_s),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPEN (up_enb_int),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.DRPRDY (up_ready_s),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPWE (up_wr_int),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.GTGREFCLK0 (1'h0),
.GTGREFCLK1 (1'h0),
.GTNORTHREFCLK00 (1'h0),
.GTNORTHREFCLK01 (1'h0),
.GTNORTHREFCLK10 (1'h0),
.GTNORTHREFCLK11 (1'h0),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.GTREFCLK00 (qpll_ref_clk),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.GTREFCLK01 (1'h0),
.GTREFCLK10 (1'h0),
.GTREFCLK11 (1'h0),
.GTSOUTHREFCLK00 (1'h0),
.GTSOUTHREFCLK01 (1'h0),
.GTSOUTHREFCLK10 (1'h0),
.GTSOUTHREFCLK11 (1'h0),
.PMARSVD0 (8'h0),
.PMARSVD1 (8'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLL0CLKRSVD0 (1'h0),
.QPLL0CLKRSVD1 (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.QPLL0FBCLKLOST (),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.QPLL0LOCK (qpll2ch_locked),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'h1),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.QPLL0OUTCLK (qpll2ch_clk),
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLL0PD (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.QPLL0REFCLKLOST (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLL0REFCLKSEL (3'h1),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'h0),
.QPLL1CLKRSVD1 (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.QPLL1FBCLKLOST (),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1LOCK (qpll1_locked),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'h1),
.QPLL1OUTCLK (qpll1_clk),
.QPLL1OUTREFCLK (qpll1_ref_clk),
.QPLL1PD (~qpll_sel),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.QPLL1REFCLKLOST (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLL1REFCLKSEL (3'h1),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1RESET (up_qpll_rst),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLLRSVD1 (8'h0),
.QPLLRSVD2 (5'h0),
.QPLLRSVD3 (5'h0),
.QPLLRSVD4 (8'h0),
.RCALENB (1'h1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0_SEL (),
.RXRECCLK1_SEL ());
end
endgenerate
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
generate
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
GTHE4_COMMON #(
.AEN_QPLL0_FBDIV (1'b1),
.AEN_QPLL1_FBDIV (1'b1),
.AEN_SDM0TOGGLE (1'b0),
.AEN_SDM1TOGGLE (1'b0),
.A_SDM0TOGGLE (1'b0),
.A_SDM1DATA_HIGH (9'b000000000),
.A_SDM1DATA_LOW (16'b0000000000000000),
.A_SDM1TOGGLE (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000100100100),
.BIAS_CFG3 (16'b0000000001000001),
.BIAS_CFG4 (16'b0000000000010000),
.BIAS_CFG_RSVD (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
util_adxcvr: Add GTH parameters for line rate of 15Gbps
2018-11-29 15:31:29 +00:00
.POR_CFG (POR_CFG),
.PPF0_CFG (PPF0_CFG),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.PPF1_CFG (16'b0000011000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL0CLKOUT_RATE ("HALF"),
util_adxcvr: Expose QPLL and CPLL *_CFG attributes
2018-10-02 14:19:35 +00:00
.QPLL0_CFG0 (QPLL_CFG0),
.QPLL0_CFG1 (QPLL_CFG1),
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
.QPLL0_CFG2 (QPLL_CFG2),
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
.QPLL0_CFG3 (QPLL_CFG3),
.QPLL0_CFG4 (QPLL_CFG4),
util_adxcvr: Add GTH parameters for line rate of 15Gbps
2018-11-29 15:31:29 +00:00
.QPLL0_CP (QPLL_CP),
.QPLL0_CP_G3 (QPLL_CP_G3),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (160),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.QPLL0_INIT_CFG0 (16'b0000001010110010),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
util_adxcvr: Add GTH parameters for line rate of 15Gbps
2018-11-29 15:31:29 +00:00
.QPLL0_LPF (QPLL_LPF),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.QPLL0_SDM_CFG0 (16'b0000000010000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL1CLKOUT_RATE ("HALF"),
util_adxcvr: Expose QPLL and CPLL *_CFG attributes
2018-10-02 14:19:35 +00:00
.QPLL1_CFG0 (QPLL_CFG0),
.QPLL1_CFG1 (QPLL_CFG1),
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
.QPLL1_CFG2 (QPLL_CFG2),
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
.QPLL1_CFG3 (QPLL_CFG3),
.QPLL1_CFG4 (QPLL_CFG4),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL1_CP (10'b1111111111),
.QPLL1_CP_G3 (10'b0011111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.QPLL1_INIT_CFG0 (16'b0000001010110010),
.QPLL1_INIT_CFG1 (8'b00000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL1_LPF (10'b0100110101),
.QPLL1_LPF_G3 (10'b0111010100),
.QPLL1_PCI_EN (1'b0),
.QPLL1_RATE_SW_USE_DRP (1'b1),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.QPLL1_SDM_CFG0 (16'b0000000010000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_ENB (1'b0),
.SARC_SEL (1'b0),
.SDM0INITSEED0_0 (16'b0000000100010001),
.SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001),
.SIM_MODE ("FAST"),
util_adxcvr- 2016.4 gthe4 updates
2017-05-18 18:49:18 +00:00
.SIM_RESET_SPEEDUP ("TRUE"))
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
i_gthe4_common (
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'd1),
.DRPADDR ({4'd0, up_addr_int}),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPWE (up_wr_int),
.GTGREFCLK0 (1'd0),
.GTGREFCLK1 (1'd0),
.GTNORTHREFCLK00 (1'd0),
.GTNORTHREFCLK01 (1'd0),
.GTNORTHREFCLK10 (1'd0),
.GTNORTHREFCLK11 (1'd0),
.GTREFCLK00 (qpll_ref_clk),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.GTREFCLK01 (qpll_ref_clk),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.GTREFCLK10 (1'd0),
.GTREFCLK11 (1'd0),
.GTSOUTHREFCLK00 (1'd0),
.GTSOUTHREFCLK01 (1'd0),
.GTSOUTHREFCLK10 (1'd0),
.GTSOUTHREFCLK11 (1'd0),
.PCIERATEQPLL0 (3'd0),
.PCIERATEQPLL1 (3'd0),
.PMARSVD0 (8'd0),
.PMARSVD1 (8'd0),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLL0CLKRSVD0 (1'd0),
.QPLL0CLKRSVD1 (1'd0),
.QPLL0FBCLKLOST (),
.QPLL0FBDIV (8'd0),
.QPLL0LOCK (qpll2ch_locked),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'd1),
.QPLL0OUTCLK (qpll2ch_clk),
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL0PD (qpll_sel),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL0REFCLKLOST (),
.QPLL0REFCLKSEL (3'b001),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'd0),
.QPLL1CLKRSVD1 (1'd0),
.QPLL1FBCLKLOST (),
.QPLL1FBDIV (8'd0),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1LOCK (qpll1_locked),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'd1),
.QPLL1OUTCLK (qpll1_clk),
.QPLL1OUTREFCLK (qpll1_ref_clk),
.QPLL1PD (~qpll_sel),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLL1REFCLKLOST (),
.QPLL1REFCLKSEL (3'b001),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1RESET (up_qpll_rst),
util_adxcvr- ultrascale+ initial commit
2016-10-03 20:11:15 +00:00
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLLRSVD1 (8'd0),
.QPLLRSVD2 (5'd0),
.QPLLRSVD3 (5'd0),
.QPLLRSVD4 (8'd0),
.RCALENB (1'd1),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0SEL (),
.RXRECCLK1SEL (),
.SDM0DATA (25'd0),
.SDM0FINALOUT (),
.SDM0RESET (1'd0),
.SDM0TESTDATA (),
.SDM0TOGGLE (1'd0),
.SDM0WIDTH (2'd0),
.SDM1DATA (25'd0),
.SDM1FINALOUT (),
.SDM1RESET (1'd0),
.SDM1TESTDATA (),
.SDM1TOGGLE (1'd0),
.SDM1WIDTH (2'd0),
.TCONGPI (10'd0),
.TCONGPO (),
.TCONPOWERUP (1'd0),
.TCONRESET (2'd0),
.TCONRSVDIN1 (2'd0),
.TCONRSVDOUT0 ());
end
endgenerate
axi/util_adxcvr: Add GTYE4 transceiver support
2019-02-11 17:15:51 +00:00
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
GTYE4_COMMON #(
.AEN_QPLL0_FBDIV (1'b1),
.AEN_QPLL1_FBDIV (1'b1),
.AEN_SDM0TOGGLE (1'b0),
.AEN_SDM1TOGGLE (1'b0),
.A_SDM0TOGGLE (1'b0),
.A_SDM1DATA_HIGH (9'b000000000),
.A_SDM1DATA_LOW (16'b0000000000000000),
.A_SDM1TOGGLE (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000100100100),
.BIAS_CFG3 (16'b0000000001000001),
.BIAS_CFG4 (16'b0000000000010000),
.BIAS_CFG_RSVD (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000000),
util_adxcvr: Expose GTY4 parameters required for 15Gbps link These parameters must be overwritten when the link is at 15Gbps. The parameters have a GTY4_ prefix since the same parameters are shared between GTY4 and GTH4 having different default values.
2019-04-15 07:59:06 +00:00
.PPF0_CFG (GTY4_PPF0_CFG),
axi/util_adxcvr: Add GTYE4 transceiver support
2019-02-11 17:15:51 +00:00
.PPF1_CFG (16'b0000011000000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (QPLL_CFG0),
.QPLL0_CFG1 (QPLL_CFG1),
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
.QPLL0_CFG2 (QPLL_CFG2),
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
.QPLL0_CFG3 (QPLL_CFG3),
.QPLL0_CFG4 (QPLL_CFG4),
.QPLL0_CP (10'b0011111111),
.QPLL0_CP_G3 (10'b0000001111),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (160),
.QPLL0_INIT_CFG0 (16'b0000001010110010),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_LPF (10'b1101111111),
.QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL0_SDM_CFG0 (16'b0000000010000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1CLKOUT_RATE ("HALF"),
.QPLL1_CFG0 (QPLL_CFG0),
.QPLL1_CFG1 (QPLL_CFG1),
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
.QPLL1_CFG2 (QPLL_CFG2),
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
.QPLL1_CFG3 (QPLL_CFG3),
.QPLL1_CFG4 (QPLL_CFG4),
.QPLL1_CP (10'b0011111111),
.QPLL1_CP_G3 (10'b0001111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'b0000001010110010),
.QPLL1_INIT_CFG1 (8'b00000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_LPF (10'b1000011111),
.QPLL1_LPF_G3 (10'b0111010100),
.QPLL1_PCI_EN (1'b0),
.QPLL1_RATE_SW_USE_DRP (1'b1),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_SDM_CFG0 (16'b0000000010000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_ENB (1'b0),
.SARC_SEL (1'b0),
.SDM0INITSEED0_0 (16'b0000000100010001),
.SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.UB_CFG0 (16'b0000000000000000),
.UB_CFG1 (16'b0000000000000000),
.UB_CFG2 (16'b0000000000000000),
.UB_CFG3 (16'b0000000000000000),
.UB_CFG4 (16'b0000000000000000),
.UB_CFG5 (16'b0000010000000000),
.UB_CFG6 (16'b0000000000000000))
i_gtye4_common (
.BGBYPASSB (1'b1),
.BGMONITORENB (1'b1),
.BGPDB (1'b1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'b1),
.DRPADDR ({4'd0, up_addr_int}),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPEN (up_enb_int),
.DRPWE (up_wr_int),
.GTGREFCLK0 (1'b0),
.GTGREFCLK1 (1'b0),
.GTNORTHREFCLK00 (1'b0),
.GTNORTHREFCLK01 (1'b0),
.GTNORTHREFCLK10 (1'b0),
.GTNORTHREFCLK11 (1'b0),
.GTREFCLK00 (qpll_ref_clk),
.GTREFCLK01 (qpll_ref_clk),
.GTREFCLK10 (1'b0),
.GTREFCLK11 (1'b0),
.GTSOUTHREFCLK00 (1'b0),
.GTSOUTHREFCLK01 (1'b0),
.GTSOUTHREFCLK10 (1'b0),
.GTSOUTHREFCLK11 (1'b0),
.PCIERATEQPLL0 (3'b0),
.PCIERATEQPLL1 (3'b0),
.PMARSVD0 (8'b0),
.PMARSVD1 (8'b0),
.QPLL0CLKRSVD0 (1'b0),
.QPLL0CLKRSVD1 (1'b0),
.QPLL0FBDIV (8'b0),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'b1),
.QPLL0PD (qpll_sel),
.QPLL0REFCLKSEL (3'b1),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'b0),
.QPLL1CLKRSVD1 (1'b0),
.QPLL1FBDIV (8'b0),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'b1),
.QPLL1PD (~qpll_sel),
.QPLL1REFCLKSEL (3'b1),
.QPLL1RESET (up_qpll_rst),
.QPLLRSVD1 (8'b0),
.QPLLRSVD2 (5'b0),
.QPLLRSVD3 (5'b0),
.QPLLRSVD4 (8'b0),
.RCALENB (1'b1),
.SDM0DATA (25'b0),
.SDM0RESET (1'b0),
.SDM0TOGGLE (1'b0),
.SDM0WIDTH (2'b0),
.SDM1DATA (25'b0),
.SDM1RESET (1'b0),
.SDM1TOGGLE (1'b0),
.SDM1WIDTH (2'b0),
.UBCFGSTREAMEN (1'b0),
.UBDO (16'b0),
.UBDRDY (1'b0),
.UBENABLE (1'b0),
.UBGPI (2'b0),
.UBINTR (2'b0),
.UBIOLMBRST (1'b0),
.UBMBRST (1'b0),
.UBMDMCAPTURE (1'b0),
.UBMDMDBGRST (1'b0),
.UBMDMDBGUPDATE (1'b0),
.UBMDMREGEN (4'b0),
.UBMDMSHIFT (1'b0),
.UBMDMSYSRST (1'b0),
.UBMDMTCK (1'b0),
.UBMDMTDI (1'b0),
.DRPDO ( up_rdata_s),
.DRPRDY ( up_ready_s),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLL0FBCLKLOST (),
.QPLL0LOCK ( qpll2ch_locked),
.QPLL0OUTCLK ( qpll2ch_clk),
.QPLL0OUTREFCLK ( qpll2ch_ref_clk),
.QPLL0REFCLKLOST (),
.QPLL1FBCLKLOST (),
.QPLL1LOCK ( qpll1_locked),
.QPLL1OUTCLK ( qpll1_clk),
.QPLL1OUTREFCLK ( qpll1_ref_clk),
.QPLL1REFCLKLOST (),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0SEL (),
.RXRECCLK1SEL (),
.SDM0FINALOUT (),
.SDM0TESTDATA (),
.SDM1FINALOUT (),
.SDM1TESTDATA (),
.UBDADDR (),
.UBDEN (),
.UBDI (),
.UBDWE (),
.UBMDMTDO (),
.UBRSVDOUT (),
.UBTXUART ());
end
endgenerate
util_adxcvr- added
2016-06-14 16:18:56 +00:00
endmodule
// ***************************************************************************
// ***************************************************************************