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pluto_hdl_adi/library/xilinx/common/ad_rst_constr.xdc

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ad_axi_ip_constr: Split up this constraint file into separate files For experimentation, to solve a constraint scoping issue, split up the ad_axi_ip_constraint file into separate constraints file, in function of there parent module.
2017-03-29 15:31:40 +00:00
ad_rst: All the synchronization registers have to have ASYNC_REG TRUE
2018-08-09 14:31:54 +00:00
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rst_async_d*_reg}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rst_sync_reg}]
ad_axi_ip_constr: Split up this constraint file into separate files For experimentation, to solve a constraint scoping issue, split up the ad_axi_ip_constraint file into separate constraints file, in function of there parent module.
2017-03-29 15:31:40 +00:00
ad_rst: Update the reset synchronizer module For a proper reset synchronization, the asynchronous reset signal should be connected to the reset pins of the two synchronizer flop, and the data input of the first flop should be connected to VCC. In the first stage we're synchronizing just the reset de-assertion, avoiding the scenario when different parts of the design are reseting at different time, causing unwanted behaviours. In the second stage we're synchronizing the reset assertion. The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW (rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.
2018-07-18 14:15:20 +00:00
set_false_path -to [get_pins *rst_sync_reg/PRE]
set_false_path -to [get_pins *rst_async_d1_reg/PRE]
set_false_path -to [get_pins *rst_async_d2_reg/PRE]
ad_axi_ip_constr: Split up this constraint file into separate files For experimentation, to solve a constraint scoping issue, split up the ad_axi_ip_constraint file into separate constraints file, in function of there parent module.
2017-03-29 15:31:40 +00:00