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pluto_hdl_adi/projects/m2k/common/m2k_bd.tcl

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M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: standalone: Disable DMA debug registers The debug register logic for the DMA take up a fair amount of resources. Disabling them frees up space in the FPGA and also helps a bit with power. Since those registers are mainly useful in development and not so much in production the change shouldn't have any visible external effects. It is possible to re-enable the debug registers by setting DEBUG_BUILD=1. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 15:43:40 +00:00
if {[info exists DEBUG_BUILD] == 0} {
set DEBUG_BUILD 1
}
set DISABLE_DMAC_DEBUG [expr !$DEBUG_BUILD]
M2K: initial commit
2017-01-31 14:43:40 +00:00
create_bd_port -dir I -from 15 -to 0 data_i
create_bd_port -dir I -from 1 -to 0 trigger_i
create_bd_port -dir O -from 15 -to 0 data_o
create_bd_port -dir O -from 15 -to 0 data_t
create_bd_port -dir O -from 1 -to 0 trigger_o
create_bd_port -dir O -from 1 -to 0 trigger_t
create_bd_port -dir I rx_clk
create_bd_port -dir I rxiq
create_bd_port -dir I -from 11 -to 0 rxd
m2k: Updated project to use new tx path with serdes
2017-03-29 07:31:16 +00:00
create_bd_port -dir I tx_clk
M2K: initial commit
2017-01-31 14:43:40 +00:00
create_bd_port -dir O txiq
create_bd_port -dir O -from 11 -to 0 txd
m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-27 14:53:38 +00:00
# AXI control interface and logic analyzer DMA (FCLK0): 27.8 MHz
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
# Logic analyzer (FCLK2): 100 MHz
m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-27 14:53:38 +00:00
# Converter DMA (FCLK3): 55.6 MHz
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK3_PORT 1
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 27.778
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ 55.556
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
m2k: Add cascading support -remove util_extract -instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths -move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-03-08 16:24:48 +00:00
#ad_connect logic_analyzer_clk_in sys_ps7/FCLK_CLK2
m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-27 14:53:38 +00:00
ad_connect converter_dma_clk sys_ps7/FCLK_CLK3
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_instance axi_logic_analyzer logic_analyzer
ad_ip_instance util_var_fifo la_trigger_fifo
ad_ip_parameter la_trigger_fifo CONFIG.DATA_WIDTH 16
ad_ip_parameter la_trigger_fifo CONFIG.ADDRESS_WIDTH 13
ad_ip_instance blk_mem_gen bram_la
ad_ip_parameter bram_la CONFIG.use_bram_block {Stand_Alone}
ad_ip_parameter bram_la CONFIG.Memory_Type {Simple_Dual_Port_RAM}
ad_ip_parameter bram_la CONFIG.Assume_Synchronous_Clk {true}
ad_ip_parameter bram_la CONFIG.Algorithm {Low_Power}
ad_ip_parameter bram_la CONFIG.Use_Byte_Write_Enable {false}
ad_ip_parameter bram_la CONFIG.Operating_Mode_A {NO_CHANGE}
ad_ip_parameter bram_la CONFIG.Register_PortB_Output_of_Memory_Primitives {true}
ad_ip_parameter bram_la CONFIG.Port_B_Clock {100}
ad_ip_parameter bram_la CONFIG.Port_B_Enable_Rate {100}
ad_ip_parameter bram_la CONFIG.Write_Width_A {16}
ad_ip_parameter bram_la CONFIG.Write_Width_B {16}
ad_ip_parameter bram_la CONFIG.Read_Width_B {16}
ad_ip_parameter bram_la CONFIG.Write_Depth_A {8192}
ad_ip_instance axi_dmac logic_analyzer_dmac
ad_ip_parameter logic_analyzer_dmac CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter logic_analyzer_dmac CONFIG.DMA_AXI_PROTOCOL_DEST 1
ad_ip_parameter logic_analyzer_dmac CONFIG.SYNC_TRANSFER_START true
ad_ip_parameter logic_analyzer_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
ad_ip_instance axi_dmac pattern_generator_dmac
ad_ip_parameter pattern_generator_dmac CONFIG.DMA_TYPE_DEST 2
ad_ip_parameter pattern_generator_dmac CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter pattern_generator_dmac CONFIG.MAX_BYTES_PER_BURST 128
ad_ip_parameter pattern_generator_dmac CONFIG.DMA_AXI_PROTOCOL_SRC 1
ad_ip_parameter pattern_generator_dmac CONFIG.DMA_DATA_WIDTH_DEST 16
ad_ip_parameter pattern_generator_dmac CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter pattern_generator_dmac CONFIG.CYCLIC true
ad_ip_parameter pattern_generator_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
ad_ip_instance axi_ad9963 axi_ad9963
ad_ip_parameter axi_ad9963 CONFIG.DAC_DATAPATH_DISABLE 1
m2k: Add scale correction option. Update parameters
2017-05-24 12:59:24 +00:00
ad_ip_parameter axi_ad9963 CONFIG.ADC_USERPORTS_DISABLE 1
ad_ip_parameter axi_ad9963 CONFIG.ADC_DATAFORMAT_DISABLE 1
ad_ip_parameter axi_ad9963 CONFIG.ADC_DCFILTER_DISABLE 1
m2k: Move ADC hardware gain correction from the AD9963 IP to AXI_ADC_DECIMATE IP
2017-08-04 11:29:27 +00:00
ad_ip_parameter axi_ad9963 CONFIG.ADC_IQCORRECTION_DISABLE 1
m2k: Add scale correction option. Update parameters
2017-05-24 12:59:24 +00:00
ad_ip_parameter axi_ad9963 CONFIG.ADC_SCALECORRECTION_ONLY 1
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_instance util_var_fifo adc_trigger_fifo
ad_ip_parameter adc_trigger_fifo CONFIG.DATA_WIDTH 32
ad_ip_parameter adc_trigger_fifo CONFIG.ADDRESS_WIDTH 13
ad_ip_instance blk_mem_gen bram_adc
ad_ip_parameter bram_adc CONFIG.use_bram_block {Stand_Alone}
ad_ip_parameter bram_adc CONFIG.Memory_Type {Simple_Dual_Port_RAM}
ad_ip_parameter bram_adc CONFIG.Assume_Synchronous_Clk true
ad_ip_parameter bram_adc CONFIG.Algorithm {Low_Power}
ad_ip_parameter bram_adc CONFIG.Enable_32bit_Address false
ad_ip_parameter bram_adc CONFIG.Use_Byte_Write_Enable false
ad_ip_parameter bram_adc CONFIG.Operating_Mode_A {NO_CHANGE}
ad_ip_parameter bram_adc CONFIG.Register_PortB_Output_of_Memory_Primitives true
ad_ip_parameter bram_adc CONFIG.Port_B_Clock 100
ad_ip_parameter bram_adc CONFIG.Port_B_Enable_Rate 100
ad_ip_parameter bram_adc CONFIG.Write_Width_A 32
ad_ip_parameter bram_adc CONFIG.Write_Width_B 32
ad_ip_parameter bram_adc CONFIG.Read_Width_B 32
ad_ip_parameter bram_adc CONFIG.Write_Depth_A 8192
m2k: Remove channel pack core for now We always have both ADC channels enabled and the cpack core takes up a fair amount of space, so remove it for now. Might come back later when we really need it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-24 14:03:58 +00:00
# FIXME: Bring this back eventually
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
#ad_ip_instance util_cpack util_cpack_ad9963
#ad_ip_parameter util_cpack_ad9963 CONFIG.NUM_OF_CHANNELS 2
#ad_ip_parameter util_cpack_ad9963 CONFIG.CHANNEL_DATA_WIDTH 16
m2k: Remove channel pack core for now We always have both ADC channels enabled and the cpack core takes up a fair amount of space, so remove it for now. Might come back later when we really need it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-24 14:03:58 +00:00
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 ad9963_adc_concat
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_instance axi_dmac ad9963_adc_dmac
ad_ip_parameter ad9963_adc_dmac CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter ad9963_adc_dmac CONFIG.DMA_AXI_PROTOCOL_DEST 1
ad_ip_parameter ad9963_adc_dmac CONFIG.SYNC_TRANSFER_START true
ad_ip_parameter ad9963_adc_dmac CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
ad_ip_instance axi_dmac ad9963_dac_dmac_a
m2k: use DMA streaming interface The previous mechanism was "probing" the DMAs for valid data. Better said, each interpolation channel enabled it's DMA until a valid data was received, then it disabled the DMA read and waited for the adjacent channel(DMA) to receive a valid data. Only when for both channels had valid data on the DMAs interfaces was the transmission started. This added an undesired and redundant complexity to the interpolation channels. Furthermore, for continuous transmission, using the above mechanism lead to a fixed phase(sample) shift between the two channels at each start. By using the streaming mechanism the interface is simplified and the above problems are solved.
2020-02-27 11:20:06 +00:00
ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_DEST 1
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_AXI_PROTOCOL_SRC 1
ad_ip_parameter ad9963_dac_dmac_a CONFIG.MAX_BYTES_PER_BURST 128
ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_DATA_WIDTH_DEST 16
ad_ip_parameter ad9963_dac_dmac_a CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter ad9963_dac_dmac_a CONFIG.CYCLIC {true}
ad_ip_parameter ad9963_dac_dmac_a CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
ad_ip_instance axi_dmac ad9963_dac_dmac_b
m2k: use DMA streaming interface The previous mechanism was "probing" the DMAs for valid data. Better said, each interpolation channel enabled it's DMA until a valid data was received, then it disabled the DMA read and waited for the adjacent channel(DMA) to receive a valid data. Only when for both channels had valid data on the DMAs interfaces was the transmission started. This added an undesired and redundant complexity to the interpolation channels. Furthermore, for continuous transmission, using the above mechanism lead to a fixed phase(sample) shift between the two channels at each start. By using the streaming mechanism the interface is simplified and the above problems are solved.
2020-02-27 11:20:06 +00:00
ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_DEST 1
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_AXI_PROTOCOL_SRC 1
ad_ip_parameter ad9963_dac_dmac_b CONFIG.MAX_BYTES_PER_BURST 128
ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_DATA_WIDTH_DEST 16
ad_ip_parameter ad9963_dac_dmac_b CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter ad9963_dac_dmac_b CONFIG.CYCLIC {true}
ad_ip_parameter ad9963_dac_dmac_b CONFIG.DISABLE_DEBUG_REGISTERS $DISABLE_DMAC_DEBUG
ad_ip_instance axi_adc_trigger adc_trigger
ad_ip_instance axi_adc_decimate axi_adc_decimate
m2k: Move ADC hardware gain correction from the AD9963 IP to AXI_ADC_DECIMATE IP
2017-08-04 11:29:27 +00:00
ad_ip_parameter axi_adc_decimate CONFIG.CORRECTION_DISABLE {0}
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_instance axi_dac_interpolate axi_dac_interpolate
m2k: Enable correction for the interpolation module
2017-08-03 14:24:26 +00:00
ad_ip_parameter axi_dac_interpolate CONFIG.CORRECTION_DISABLE {0}
m2k: ip automatic version update
2017-04-18 12:12:07 +00:00
ad_ip_instance proc_sys_reset logic_analyzer_reset
ad_ip_instance axi_rd_wr_combiner axi_rd_wr_combiner_logic
ad_ip_instance axi_rd_wr_combiner axi_rd_wr_combiner_converter
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 10:02:11 +00:00
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect data_i logic_analyzer/data_i
ad_connect trigger_i logic_analyzer/trigger_i
ad_connect data_o logic_analyzer/data_o
ad_connect data_t logic_analyzer/data_t
m2k: Add cascading support -remove util_extract -instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths -move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-03-08 16:24:48 +00:00
ad_connect axi_ad9963/adc_clk logic_analyzer/clk
m2k: Connect logic_analyzer path to clk_out instead of clk - this allows for the clock switching to be done inside axi_logic_analyzer core
2017-03-31 09:29:29 +00:00
ad_connect logic_analyzer_clk logic_analyzer/clk_out
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
ad_connect logic_analyzer_clk pattern_generator_dmac/fifo_rd_clk
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
ad_connect logic_analyzer_clk la_trigger_fifo/clk
m2k: Move the BRAM generation outside of the variable fifo IP
2017-04-10 11:07:19 +00:00
ad_connect logic_analyzer_clk bram_la/clkb
ad_connect logic_analyzer_clk bram_la/clka
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
ad_connect logic_analyzer_clk logic_analyzer_dmac/fifo_wr_clk
ad_connect logic_analyzer_clk logic_analyzer_reset/slowest_sync_clk
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 10:02:11 +00:00
ad_connect logic_analyzer_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect logic_analyzer_reset/bus_struct_reset la_trigger_fifo/rst
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect la_trigger_fifo/data_in logic_analyzer/adc_data
ad_connect la_trigger_fifo/data_in_valid logic_analyzer/adc_valid
m2k: Move the BRAM generation outside of the variable fifo IP
2017-04-10 11:07:19 +00:00
ad_connect bram_la/addra la_trigger_fifo/addr_w
ad_connect bram_la/dina la_trigger_fifo/din_w
ad_connect bram_la/ena la_trigger_fifo/en_w
ad_connect bram_la/wea la_trigger_fifo/wea_w
ad_connect bram_la/addrb la_trigger_fifo/addr_r
ad_connect bram_la/doutb la_trigger_fifo/dout_r
ad_connect bram_la/enb la_trigger_fifo/en_r
ad_connect logic_analyzer_dmac/fifo_wr_din la_trigger_fifo/data_out
ad_connect logic_analyzer_dmac/fifo_wr_en la_trigger_fifo/data_out_valid
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Updated project to work with the fifo_depth related changes
2017-06-06 12:37:23 +00:00
ad_connect logic_analyzer/fifo_depth la_trigger_fifo/depth
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect logic_analyzer/trigger_out logic_analyzer_dmac/fifo_wr_sync
m2k: Add cascading support -remove util_extract -instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths -move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-03-08 16:24:48 +00:00
ad_connect logic_analyzer/trigger_in adc_trigger/trigger_out_la
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect pattern_generator_dmac/fifo_rd_en logic_analyzer/dac_read
ad_connect pattern_generator_dmac/fifo_rd_dout logic_analyzer/dac_data
ad_connect pattern_generator_dmac/fifo_rd_valid logic_analyzer/dac_valid
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-03-29 08:03:00 +00:00
ad_connect axi_ad9963/adc_clk adc_trigger_fifo/clk
m2k: Remove channel pack core for now We always have both ADC channels enabled and the cpack core takes up a fair amount of space, so remove it for now. Might come back later when we really need it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-24 14:03:58 +00:00
#ad_connect axi_ad9963/adc_clk util_cpack_ad9963/adc_clk
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-03-29 08:03:00 +00:00
ad_connect axi_adc_decimate/adc_clk axi_ad9963/adc_clk
m2k: Connected adc/dac resets to decimation/interpolation cores
2017-03-29 09:07:44 +00:00
ad_connect axi_adc_decimate/adc_rst axi_ad9963/adc_rst
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-03-29 08:03:00 +00:00
ad_connect ad9963_adc_dmac/fifo_wr_clk axi_ad9963/adc_clk
m2k: Move the BRAM generation outside of the variable fifo IP
2017-04-10 11:07:19 +00:00
ad_connect bram_adc/clka axi_ad9963/adc_clk
ad_connect bram_adc/clkb axi_ad9963/adc_clk
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Remove channel pack core for now We always have both ADC channels enabled and the cpack core takes up a fair amount of space, so remove it for now. Might come back later when we really need it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-24 14:03:58 +00:00
#ad_connect axi_ad9963/adc_rst util_cpack_ad9963/adc_rst
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-03-29 08:03:00 +00:00
ad_connect axi_ad9963/adc_rst adc_trigger_fifo/rst
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect axi_adc_decimate/adc_data_a axi_ad9963/adc_data_i
ad_connect axi_adc_decimate/adc_data_b axi_ad9963/adc_data_q
ad_connect axi_adc_decimate/adc_valid_a axi_ad9963/adc_valid_i
ad_connect axi_adc_decimate/adc_valid_b axi_ad9963/adc_valid_q
m2k: Remove channel pack core for now We always have both ADC channels enabled and the cpack core takes up a fair amount of space, so remove it for now. Might come back later when we really need it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-24 14:03:58 +00:00
#ad_connect axi_ad9963/adc_enable_i util_cpack_ad9963/adc_enable_0
#ad_connect adc_trigger/data_valid_a_trig util_cpack_ad9963/adc_valid_0
#ad_connect adc_trigger/data_a_trig util_cpack_ad9963/adc_data_0
#ad_connect axi_ad9963/adc_enable_q util_cpack_ad9963/adc_enable_1
#ad_connect adc_trigger/data_valid_b_trig util_cpack_ad9963/adc_valid_1
#ad_connect adc_trigger/data_b_trig util_cpack_ad9963/adc_data_1
#ad_connect adc_trigger_fifo/data_in util_cpack_ad9963/adc_data
#ad_connect adc_trigger_fifo/data_in_valid util_cpack_ad9963/adc_valid
#ad_connect util_cpack_ad9963/adc_data adc_trigger_extract/data_in_trigger
m2k: Move the BRAM generation outside of the variable fifo IP
2017-04-10 11:07:19 +00:00
ad_connect adc_trigger_fifo/din_w bram_adc/dina
ad_connect adc_trigger_fifo/en_w bram_adc/ena
ad_connect adc_trigger_fifo/wea_w bram_adc/wea
ad_connect adc_trigger_fifo/addr_w bram_adc/addra
ad_connect bram_adc/addrb adc_trigger_fifo/addr_r
ad_connect bram_adc/doutb adc_trigger_fifo/dout_r
ad_connect bram_adc/enb adc_trigger_fifo/en_r
m2k: Remove channel pack core for now We always have both ADC channels enabled and the cpack core takes up a fair amount of space, so remove it for now. Might come back later when we really need it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-24 14:03:58 +00:00
ad_connect adc_trigger/data_a_trig ad9963_adc_concat/In0
ad_connect adc_trigger/data_b_trig ad9963_adc_concat/In1
ad_connect adc_trigger/data_valid_a_trig adc_trigger_fifo/data_in_valid
ad_connect ad9963_adc_concat/dout adc_trigger_fifo/data_in
m2k: Connect the adc_trigger reset
2019-11-12 15:10:29 +00:00
ad_connect axi_ad9963/adc_rst adc_trigger/reset
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Add cascading support -remove util_extract -instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths -move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-03-08 16:24:48 +00:00
ad_connect adc_trigger_fifo/depth adc_trigger/fifo_depth
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Add cascading support -remove util_extract -instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths -move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-03-08 16:24:48 +00:00
ad_connect adc_trigger/trigger_in logic_analyzer/trigger_out_adc
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Add cascading support -remove util_extract -instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths -move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-03-08 16:24:48 +00:00
ad_connect adc_trigger_fifo/data_out ad9963_adc_dmac/fifo_wr_din
ad_connect adc_trigger/trigger_out ad9963_adc_dmac/fifo_wr_sync
ad_connect adc_trigger_fifo/data_out_valid ad9963_adc_dmac/fifo_wr_en
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect axi_dac_interpolate/dac_clk axi_ad9963/dac_clk
m2k: Connected adc/dac resets to decimation/interpolation cores
2017-03-29 09:07:44 +00:00
ad_connect axi_dac_interpolate/dac_rst axi_ad9963/dac_rst
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect axi_dac_interpolate/dac_valid_a axi_ad9963/dac_valid_i
ad_connect axi_dac_interpolate/dac_valid_b axi_ad9963/dac_valid_q
ad_connect axi_dac_interpolate/dac_int_data_a axi_ad9963/dac_data_i
ad_connect axi_dac_interpolate/dac_int_data_b axi_ad9963/dac_data_q
m2k: use DMA streaming interface The previous mechanism was "probing" the DMAs for valid data. Better said, each interpolation channel enabled it's DMA until a valid data was received, then it disabled the DMA read and waited for the adjacent channel(DMA) to receive a valid data. Only when for both channels had valid data on the DMAs interfaces was the transmission started. This added an undesired and redundant complexity to the interpolation channels. Furthermore, for continuous transmission, using the above mechanism lead to a fixed phase(sample) shift between the two channels at each start. By using the streaming mechanism the interface is simplified and the above problems are solved.
2020-02-27 11:20:06 +00:00
ad_connect ad9963_dac_dmac_a/m_axis_aclk axi_ad9963/dac_clk
ad_connect ad9963_dac_dmac_b/m_axis_aclk axi_ad9963/dac_clk
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: use DMA streaming interface The previous mechanism was "probing" the DMAs for valid data. Better said, each interpolation channel enabled it's DMA until a valid data was received, then it disabled the DMA read and waited for the adjacent channel(DMA) to receive a valid data. Only when for both channels had valid data on the DMAs interfaces was the transmission started. This added an undesired and redundant complexity to the interpolation channels. Furthermore, for continuous transmission, using the above mechanism lead to a fixed phase(sample) shift between the two channels at each start. By using the streaming mechanism the interface is simplified and the above problems are solved.
2020-02-27 11:20:06 +00:00
ad_connect axi_dac_interpolate/dac_data_a ad9963_dac_dmac_a/m_axis_data
ad_connect axi_dac_interpolate/dma_ready_a ad9963_dac_dmac_a/m_axis_ready
ad_connect axi_dac_interpolate/dac_enable_a axi_ad9963/dac_enable_i
ad_connect ad9963_dac_dmac_a/m_axis_valid axi_dac_interpolate/dma_valid_a
ad_connect axi_dac_interpolate/dac_data_b ad9963_dac_dmac_b/m_axis_data
ad_connect axi_dac_interpolate/dma_ready_b ad9963_dac_dmac_b/m_axis_ready
ad_connect axi_dac_interpolate/dac_enable_b axi_ad9963/dac_enable_q
ad_connect ad9963_dac_dmac_b/m_axis_valid axi_dac_interpolate/dma_valid_b
M2K: initial commit
2017-01-31 14:43:40 +00:00
m2k: Use dac trigger
2019-08-19 15:38:14 +00:00
ad_connect axi_dac_interpolate/trigger_i trigger_i
ad_connect axi_dac_interpolate/trigger_adc adc_trigger/trigger_out_la
ad_connect axi_dac_interpolate/trigger_la logic_analyzer/trigger_out_adc
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect /axi_ad9963/tx_data txd
ad_connect /axi_ad9963/tx_iq txiq
ad_connect /axi_ad9963/tx_clk tx_clk
ad_connect /axi_ad9963/trx_data rxd
ad_connect /axi_ad9963/trx_clk rx_clk
ad_connect /axi_ad9963/trx_iq rxiq
ad_connect adc_trigger/data_a axi_adc_decimate/adc_dec_data_a
ad_connect adc_trigger/data_valid_a axi_adc_decimate/adc_dec_valid_a
ad_connect adc_trigger/data_b axi_adc_decimate/adc_dec_data_b
ad_connect adc_trigger/data_valid_b axi_adc_decimate/adc_dec_valid_b
m2k: Connect signals for instrument sync
2020-05-11 14:40:16 +00:00
ad_connect axi_adc_decimate/adc_dec_valid_a logic_analyzer/external_valid
ad_connect axi_adc_decimate/adc_data_rate logic_analyzer/external_rate
ad_connect axi_adc_decimate/adc_oversampling_en logic_analyzer/external_decimation_en
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-03-29 08:03:00 +00:00
ad_connect adc_trigger/clk axi_ad9963/adc_clk
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect trigger_i adc_trigger/trigger_i
ad_connect trigger_o adc_trigger/trigger_o
ad_connect trigger_t adc_trigger/trigger_t
ad_connect axi_ad9963/dac_sync_in axi_ad9963/dac_sync_out
ad_connect axi_ad9963/adc_dovf ad9963_adc_dmac/fifo_wr_overflow
m2k: use DMA streaming interface The previous mechanism was "probing" the DMAs for valid data. Better said, each interpolation channel enabled it's DMA until a valid data was received, then it disabled the DMA read and waited for the adjacent channel(DMA) to receive a valid data. Only when for both channels had valid data on the DMAs interfaces was the transmission started. This added an undesired and redundant complexity to the interpolation channels. Furthermore, for continuous transmission, using the above mechanism lead to a fixed phase(sample) shift between the two channels at each start. By using the streaming mechanism the interface is simplified and the above problems are solved.
2020-02-27 11:20:06 +00:00
ad_connect axi_ad9963/dac_dunf axi_dac_interpolate/underflow
M2K: initial commit
2017-01-31 14:43:40 +00:00
# interconnects
m2k: Replace logic analyzer MMCM The MMCM generating the logic analyzer clock unfortunately consumes a disproportionately large amount of power compared to the rest of the design. Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs. The IO PLL is running anyway so the power requirement is much lower. For the time being this means we loose the ability to source the clock from an external pin. But that feature is not supported by software at the moment anyway. We'll bring it eventually when required. This changes reduces power consumption by roughly 100mW. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-23 13:56:35 +00:00
#ad_cpu_interconnect 0x70000000 clk_generator
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_cpu_interconnect 0x70100000 logic_analyzer
ad_cpu_interconnect 0x70200000 axi_ad9963
ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac
ad_cpu_interconnect 0x7C420000 pattern_generator_dmac
ad_cpu_interconnect 0x7C440000 ad9963_adc_dmac
ad_cpu_interconnect 0x7C460000 ad9963_dac_dmac_b
ad_cpu_interconnect 0x7C480000 ad9963_dac_dmac_a
ad_cpu_interconnect 0x7C4c0000 adc_trigger
ad_cpu_interconnect 0x7C500000 axi_adc_decimate
ad_cpu_interconnect 0x7C5a0000 axi_dac_interpolate
m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-27 14:53:38 +00:00
# Logic analyzer DMA
m2k: Reduce AXI interconnect utilization Use the new axi_rd_wr_combiner module to ... the read and write DMA interfaces into a single interface. This allows the AXI interconnect completely optimize itself away and reduce the overall resource utilization of the project. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 12:05:34 +00:00
ad_connect sys_cpu_clk axi_rd_wr_combiner_logic/clk
ad_connect sys_cpu_clk logic_analyzer_dmac/m_dest_axi_aclk
ad_connect sys_cpu_clk pattern_generator_dmac/m_src_axi_aclk
ad_connect logic_analyzer_dmac/m_dest_axi axi_rd_wr_combiner_logic/s_wr_axi
ad_connect pattern_generator_dmac/m_src_axi axi_rd_wr_combiner_logic/s_rd_axi
m2k: Remove memory interconnects and connect directly to the HP ports Vivado generates errors with the smartconnect change, altough the interconnect should be synthesized out
2019-04-08 17:30:14 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK
ad_connect axi_rd_wr_combiner_logic/m_axi sys_ps7/S_AXI_HP1
m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-27 14:53:38 +00:00
# Converter DMA
ad_connect converter_dma_clk axi_rd_wr_combiner_converter/clk
ad_connect converter_dma_clk ad9963_adc_dmac/m_dest_axi_aclk
ad_connect converter_dma_clk ad9963_dac_dmac_a/m_src_axi_aclk
m2k: Reduce AXI interconnect utilization Use the new axi_rd_wr_combiner module to ... the read and write DMA interfaces into a single interface. This allows the AXI interconnect completely optimize itself away and reduce the overall resource utilization of the project. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 12:05:34 +00:00
ad_connect ad9963_adc_dmac/m_dest_axi axi_rd_wr_combiner_converter/s_wr_axi
ad_connect ad9963_dac_dmac_a/m_src_axi axi_rd_wr_combiner_converter/s_rd_axi
m2k: Remove memory interconnects and connect directly to the HP ports Vivado generates errors with the smartconnect change, altough the interconnect should be synthesized out
2019-04-08 17:30:14 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1}
ad_connect converter_dma_clk sys_ps7/S_AXI_HP2_ACLK
ad_connect axi_rd_wr_combiner_converter/m_axi sys_ps7/S_AXI_HP2
m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-27 14:53:38 +00:00
# Only 16-bit we can run at a slower clock
m2k: Remove memory interconnects and connect directly to the HP ports Vivado generates errors with the smartconnect change, altough the interconnect should be synthesized out
2019-04-08 17:30:14 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP3 {1}
ad_connect sys_cpu_clk sys_ps7/S_AXI_HP3_ACLK
ad_connect sys_cpu_clk ad9963_dac_dmac_b/m_src_axi_aclk
ad_connect ad9963_dac_dmac_b/m_src_axi sys_ps7/S_AXI_HP3
create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces ad9963_dac_dmac_b/m_src_axi] \
[get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_HP3_DDR_LOWOCM
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 11:57:50 +00:00
m2k: Reduce AXI interconnect utilization Use the new axi_rd_wr_combiner module to ... the read and write DMA interfaces into a single interface. This allows the AXI interconnect completely optimize itself away and reduce the overall resource utilization of the project. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-17 12:05:34 +00:00
# Map rd-wr combiner
assign_bd_address [get_bd_addr_segs { \
axi_rd_wr_combiner_converter/s_rd_axi/reg0 \
axi_rd_wr_combiner_converter/s_wr_axi/reg0 \
axi_rd_wr_combiner_logic/s_rd_axi/reg0 \
axi_rd_wr_combiner_logic/s_wr_axi/reg0 \
}]
set_property range 512M [get_bd_addr_segs { \
ad9963_dac_dmac_a/m_src_axi/SEG_axi_rd_wr_combiner_converter_reg0 \
ad9963_adc_dmac/m_dest_axi/SEG_axi_rd_wr_combiner_converter_reg0 \
pattern_generator_dmac/m_src_axi/SEG_axi_rd_wr_combiner_logic_reg0 \
logic_analyzer_dmac/m_dest_axi/SEG_axi_rd_wr_combiner_logic_reg0 \
}]
M2K: initial commit
2017-01-31 14:43:40 +00:00
ad_connect sys_cpu_resetn logic_analyzer_dmac/m_dest_axi_aresetn
ad_connect sys_cpu_resetn pattern_generator_dmac/m_src_axi_aresetn
ad_connect sys_cpu_resetn ad9963_adc_dmac/m_dest_axi_aresetn
ad_connect sys_cpu_resetn ad9963_dac_dmac_a/m_src_axi_aresetn
ad_connect sys_cpu_resetn ad9963_dac_dmac_b/m_src_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-12 logic_analyzer_dmac/irq
ad_cpu_interrupt ps-12 mb-13 pattern_generator_dmac/irq
ad_cpu_interrupt ps-10 mb-14 ad9963_adc_dmac/irq
ad_cpu_interrupt ps-9 mb-15 ad9963_dac_dmac_a/irq
ad_cpu_interrupt ps-8 mb-16 ad9963_dac_dmac_b/irq