2021-03-15 08:51:14 +00:00
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proc ad_data_offload_create {instance_name datapath_type mem_type mem_size source_dwidth destination_dwidth {ddr_data_width 0} {ddr_addr_width 0}} {
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global ad_hdl_dir
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global sys_cpu_resetn
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create_bd_cell -type hier $instance_name
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current_bd_instance /$instance_name
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###########################################################################
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## Sub-system's ports and interface definitions
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###########################################################################
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create_bd_pin -dir I -type clk s_axi_aclk
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create_bd_pin -dir I -type rst s_axi_aresetn
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create_bd_pin -dir I -type clk s_axis_aclk
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create_bd_pin -dir I -type rst s_axis_aresetn
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create_bd_pin -dir I -type clk m_axis_aclk
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create_bd_pin -dir I -type rst m_axis_aresetn
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
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create_bd_pin -dir I init_req
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create_bd_pin -dir O init_ack
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create_bd_pin -dir I sync_ext
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set source_max_address [expr ($mem_size * 8) / $source_dwidth]
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set source_awidth [log2 $source_max_address]
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set destination_max_address [expr ($mem_size * 8) / $destination_dwidth]
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set destination_awidth [log2 $destination_max_address]
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###########################################################################
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# Data offload controller instance
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###########################################################################
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ad_ip_instance data_offload i_data_offload [list \
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MEM_TYPE $mem_type \
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MEM_SIZE $mem_size \
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TX_OR_RXN_PATH $datapath_type \
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SRC_DATA_WIDTH $source_dwidth \
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SRC_ADDR_WIDTH $source_awidth \
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DST_DATA_WIDTH $destination_dwidth \
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DST_ADDR_WIDTH $destination_awidth \
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DST_CYCLIC_EN $datapath_type \
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]
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if {$mem_type == 0} {
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###########################################################################
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# Internal storage instance (BRAMs)
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###########################################################################
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## Add the memory module source into the project file set
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if {[get_files -quiet "ad_mem_asym.v"] == ""} {
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add_files -norecurse -fileset sources_1 "$ad_hdl_dir/library/common/ad_mem_asym.v"
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}
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create_bd_cell -type module -reference ad_mem_asym storage_unit
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set_property -dict [list \
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CONFIG.A_DATA_WIDTH $source_dwidth \
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CONFIG.A_ADDRESS_WIDTH $source_awidth \
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CONFIG.B_DATA_WIDTH $destination_dwidth \
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CONFIG.B_ADDRESS_WIDTH $destination_awidth \
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] [get_bd_cells storage_unit]
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ad_connect storage_unit/clka i_data_offload/s_axis_aclk
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ad_connect storage_unit/wea i_data_offload/fifo_src_wen
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ad_connect storage_unit/addra i_data_offload/fifo_src_waddr
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ad_connect storage_unit/dina i_data_offload/fifo_src_wdata
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ad_connect storage_unit/clkb i_data_offload/m_axis_aclk
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ad_connect storage_unit/reb i_data_offload/fifo_dst_ren
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ad_connect storage_unit/addrb i_data_offload/fifo_dst_raddr
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ad_connect storage_unit/doutb i_data_offload/fifo_dst_rdata
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2021-03-19 08:24:37 +00:00
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ad_connect i_data_offload/fifo_dst_ready VCC ; ## BRAM is always ready
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2021-03-15 08:51:14 +00:00
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ad_connect i_data_offload/ddr_calib_done VCC
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} elseif {$mem_type == 1} {
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###########################################################################
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# Bridge instance for the external DDR4 memory contreller
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# NOTE: The MIG instantiation should be in project's system_bd.tcl file
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###########################################################################
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ad_ip_instance util_fifo2axi_bridge fifo2axi_bridge [list \
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SRC_DATA_WIDTH $source_dwidth \
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SRC_ADDR_WIDTH $source_awidth \
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DST_DATA_WIDTH $destination_dwidth \
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DST_ADDR_WIDTH $destination_awidth \
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AXI_DATA_WIDTH $ddr_data_width \
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AXI_ADDR_WIDTH $ddr_addr_width \
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AXI_ADDRESS 0x00000000 \
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2021-03-23 19:21:12 +00:00
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AXI_ADDRESS_LIMIT [format 0x%X [expr int([expr { pow(2, 30) }]) - 1]] \
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2021-03-15 08:51:14 +00:00
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REMOVE_NULL_BEAT_EN $datapath_type \
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]
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ad_connect fifo2axi_bridge/fifo_src_clk i_data_offload/s_axis_aclk
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ad_connect fifo2axi_bridge/fifo_src_resetn i_data_offload/fifo_src_resetn
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ad_connect fifo2axi_bridge/fifo_src_wen i_data_offload/fifo_src_wen
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ad_connect fifo2axi_bridge/fifo_src_waddr i_data_offload/fifo_src_waddr
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ad_connect fifo2axi_bridge/fifo_src_wdata i_data_offload/fifo_src_wdata
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ad_connect fifo2axi_bridge/fifo_src_wlast i_data_offload/fifo_src_wlast
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ad_connect fifo2axi_bridge/fifo_dst_clk i_data_offload/m_axis_aclk
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ad_connect fifo2axi_bridge/fifo_dst_resetn i_data_offload/fifo_dst_resetn
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ad_connect fifo2axi_bridge/fifo_dst_ren i_data_offload/fifo_dst_ren
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ad_connect fifo2axi_bridge/fifo_dst_raddr i_data_offload/fifo_dst_raddr
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ad_connect fifo2axi_bridge/fifo_dst_rdata i_data_offload/fifo_dst_rdata
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ad_connect fifo2axi_bridge/fifo_dst_ready i_data_offload/fifo_dst_ready
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}
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###########################################################################
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# Internal connections
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###########################################################################
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ad_connect s_axi_aclk i_data_offload/s_axi_aclk
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ad_connect s_axi_aresetn i_data_offload/s_axi_aresetn
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ad_connect s_axis_aclk i_data_offload/s_axis_aclk
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ad_connect s_axis_aresetn i_data_offload/s_axis_aresetn
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ad_connect m_axis_aclk i_data_offload/m_axis_aclk
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ad_connect m_axis_aresetn i_data_offload/m_axis_aresetn
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ad_connect s_axi i_data_offload/s_axi
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ad_connect s_axis i_data_offload/s_axis
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ad_connect m_axis i_data_offload/m_axis
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ad_connect init_req i_data_offload/init_req
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ad_connect init_ack i_data_offload/init_ack
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ad_connect sync_ext i_data_offload/sync_ext
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current_bd_instance /
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}
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proc log2 {x} {
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if {$x <= 0} {error "log2 requires a positive argument"}
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if {$x < 2} {
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return $x
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} else {
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for {set i 0} {$x > 0} {incr i} {
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set x [expr $x >> 1]
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}
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return $i
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}
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}
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