2014-07-01 17:09:38 +00:00
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2014-07-02 18:56:00 +00:00
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create_clock -period "20.000 ns" -name clk_50m [get_ports {sys_clk}]
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2014-07-21 13:06:10 +00:00
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create_clock -period "3.906 ns" -name clk_250m [get_ports {rx_clk_in}]
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2014-07-02 18:56:00 +00:00
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create_clock -period "10.000 ns" -name clk_100m [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
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2014-07-01 17:09:38 +00:00
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2014-07-21 13:06:10 +00:00
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2014-07-01 17:09:38 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2014-07-21 13:06:10 +00:00
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set clk_64m [get_clocks {i_system_bd|axi_ad9361|i_ad9361|i_dev_if|i_clk|i_gclk|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set_false_path -from clk_250m -to $clk_64m
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set_false_path -from $clk_64m -to clk_250m
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2014-07-02 18:56:00 +00:00
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set_false_path -from clk_50m -to clk_100m
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2014-07-21 13:06:10 +00:00
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set_false_path -from clk_50m -to $clk_64m
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2014-07-02 18:56:00 +00:00
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set_false_path -from clk_100m -to clk_50m
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2014-07-21 13:06:10 +00:00
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set_false_path -from clk_100m -to $clk_64m
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set_false_path -from $clk_64m -to clk_50m
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set_false_path -from $clk_64m -to clk_100m
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2014-07-01 17:09:38 +00:00
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