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pluto_hdl_adi/projects/fmcomms11/zc706/system_bd.tcl

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fmcomms11: Initial commit
2018-04-13 16:09:57 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
fmcomms11: Move the FIFO address variables into system_bd These variables can vary in function of the available memory resources of the FPGA carrier board.
2019-05-30 13:45:10 +00:00
# the DAC FIFO has a 500KSMP depth - 1 Mbyte
set dac_fifo_address_width 15
# by default PLDDR is used (1 Gbyte), this varible should be ignored
set adc_fifo_address_width 18
fmcomms11: Initial commit
2018-04-13 16:09:57 +00:00
source ../common/fmcomms11_bd.tcl