2015-05-11 14:17:07 +00:00
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2015-06-01 14:59:33 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2015-05-11 14:17:07 +00:00
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derive_pll_clocks
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2015-07-13 14:07:18 +00:00
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derive_clock_uncertainty
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2015-05-11 14:17:07 +00:00
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2017-05-16 14:09:30 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
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-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_tx_csr_inst*] \
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-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_tx_ctl_inst*] \
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-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
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set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}] \
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-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk_100mhz}]
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2017-05-15 13:32:36 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
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2017-05-16 14:09:30 +00:00
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-through [get_nets *altera_jesd204_tx_csr_inst*] -to [get_clocks {sys_clk_100mhz}]
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2017-05-15 13:32:36 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
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2017-05-16 14:09:30 +00:00
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-through [get_nets *altera_jesd204_tx_ctl_inst*] -to [get_clocks {sys_clk_100mhz}]
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2017-05-15 13:32:36 +00:00
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