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pluto_hdl_adi/projects/ad9081_fmca_ebz/zcu102/system_project.tcl

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ad9081_fmca_ebz:zcu102: initial version
2019-12-05 08:59:26 +00:00
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../../scripts/adi_env.tcl
ad9081_fmca_ebz:zcu102: initial version
2019-12-05 08:59:26 +00:00
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
ad9081:zcu102: Expose parameters to environment Allow setting project parameters from the environment.
2021-01-18 07:48:47 +00:00
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1
# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1
ad9081_fmca_ebz: Added parameter description Add parameter description to project and common block design file
2020-04-21 15:16:08 +00:00
#
# Parameter description:
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
#
ad9081_fmca_ebz: Add LANE_RATE param to all projects The block design expects a lane rate to be set in the system project.
2021-04-30 15:00:26 +00:00
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
ad9081_fmca_ebz: Added parameter description Add parameter description to project and common block design file
2020-04-21 15:16:08 +00:00
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
#
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
#
ad9081_fmca_ebz: Added parameter description Add parameter description to project and common block design file
2020-04-21 15:16:08 +00:00
ad9081_fmca_ebz:zcu102: initial version
2019-12-05 08:59:26 +00:00
adi_project ad9081_fmca_ebz_zcu102 0 [list \
ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design Signed-off-by: David Winter <david.winter@analog.com>
2021-06-17 13:22:49 +00:00
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \
SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \
ad9081_fmca_ebz:zcu102: initial version
2019-12-05 08:59:26 +00:00
]
adi_project_files ad9081_fmca_ebz_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"timing_constr.xdc"\
"../../../library/common/ad_3w_spi.v"\
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
"$ad_hdl_dir/library/common/ad_iobuf.v" \
ad9081_fmca_ebz:zcu102: initial version
2019-12-05 08:59:26 +00:00
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run ad9081_fmca_ebz_zcu102