2015-06-26 09:04:19 +00:00
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2021-03-15 08:51:59 +00:00
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## Offload attributes
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2021-09-27 16:34:34 +00:00
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set adc_offload_type 1 ; ## PL_DDR
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set adc_offload_size [expr 1 * 1024 * 1024 * 1024] ; ## 1 Gbyte
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2017-02-27 21:05:21 +00:00
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2021-09-27 16:34:34 +00:00
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set dac_offload_type 0 ; ## BRAM
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set dac_offload_size [expr 1 * 1024 * 1024] ; ## 1 MByte
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2021-03-15 08:51:59 +00:00
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set plddr_offload_axi_data_width 512
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set plddr_offload_axi_addr_width 30
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2017-02-27 21:05:21 +00:00
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2021-09-27 16:34:34 +00:00
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## NOTE: With this configuration the #36Kb BRAM utilization is at ~52%
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2018-08-10 07:34:45 +00:00
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2021-03-15 08:51:59 +00:00
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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2015-06-26 09:04:19 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source ../common/daq2_bd.tcl
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2021-03-15 08:51:59 +00:00
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################################################################################
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## DDR3 MIG for Data Offload IP
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################################################################################
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if {$adc_offload_type} {
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set offload_name axi_ad9680_offload
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}
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if {$dac_offload_type} {
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set offload_name axi_ad9144_offload
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}
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if {$adc_offload_type || $dac_offload_type} {
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ad_ip_instance proc_sys_reset axi_rstgen
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ad_ip_instance mig_7series axi_ddr_cntrl
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file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \
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[get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]]
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ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj
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# PL-DDR data offload interfaces
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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create_bd_port -dir I -type rst sys_rst
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set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk
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ad_connect axi_ddr_cntrl/ui_clk $offload_name/fifo2axi_bridge/axi_clk
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ad_connect axi_ddr_cntrl/S_AXI $offload_name/fifo2axi_bridge/ddr_axi
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ad_connect axi_rstgen/peripheral_aresetn $offload_name/fifo2axi_bridge/axi_resetn
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ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn
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ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in
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assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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ad_connect sys_clk axi_ddr_cntrl/SYS_CLK
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ad_connect ddr3 axi_ddr_cntrl/DDR3
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ad_connect axi_ddr_cntrl/device_temp_i GND
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ad_connect $offload_name/i_data_offload/ddr_calib_done axi_ddr_cntrl/init_calib_complete
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}
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################################################################################
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# System ID
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################################################################################
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2019-06-28 08:41:21 +00:00
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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2020-09-28 21:10:35 +00:00
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2021-03-15 08:51:59 +00:00
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set sys_cstring "ADC_OFFLOAD_TYPE=$adc_offload_type\nDAC_OFFLOAD_TYPE=$dac_offload_type"
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sysid_gen_sys_init_file $sys_cstring
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