zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc

35 lines
2.2 KiB
Plaintext
Raw Normal View History

Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
adcfifo: axi version
2015-04-07 20:16:17 +00:00
axi_adcfifo: Updated constraints
2015-04-30 11:23:24 +00:00
set_property ASYNC_REG TRUE \
[get_cells -hier *axi_waddr_m1_reg*] \
[get_cells -hier *axi_waddr_m2_reg*] \
axi_adcfifo_constr.xdc: Add missing backslash to command
2018-02-13 15:15:08 +00:00
[get_cells -hier *adc_xfer_req_m_reg[0]*] \
axi_adcfifo: Add missing constraints Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 09:31:07 +00:00
[get_cells -hier *axi_xfer_req_m_reg[0]*]
axi_adcfifo: Updated constraints
2015-04-30 11:23:24 +00:00
axi_adcfifo: Fix constraints to apply also to Ultrascale devices Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
2018-08-27 11:18:40 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
adcfifo: axi version
2015-04-07 20:16:17 +00:00
axi_adcfifo: Fix constraints to apply also to Ultrascale devices Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
2018-08-27 11:18:40 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *adc_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *adc_*_m* && IS_SEQUENTIAL}]
adcfifo: axi version
2015-04-07 20:16:17 +00:00
axi_adcfifo: Fix constraints to apply also to Ultrascale devices Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
2018-08-27 11:18:40 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *adc_rel_waddr* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_rel_waddr* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_waddr_rel_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_raddr_rel_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_raddr_rel_reg* && IS_SEQUENTIAL}]
adcfifo: axi version
2015-04-07 20:16:17 +00:00
axi_adcfifo: Fix constraints to apply also to Ultrascale devices Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
2018-08-27 11:18:40 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *axi_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]