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pluto_hdl_adi/library/axi_dmac/axi_dmac_hw.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
altera files
2014-03-21 19:13:50 +00:00
Update Quartus Prime version from 19.3.0 to 20.1.0 adi_project_intel.tcl: Change quartus version to 20.1.0. library: Set qsys version so that IP instances won't require a specific version.
2021-02-25 09:41:57 +00:00
package require qsys 14.0
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2018-08-14 10:08:06 +00:00
source ../scripts/adi_ip_intel.tcl
altera files
2014-03-21 19:13:50 +00:00
set_module_property NAME axi_dmac
set_module_property DESCRIPTION "AXI DMA Controller"
set_module_property VERSION 1.0
qsys- library group
2015-07-17 14:07:15 +00:00
set_module_property GROUP "Analog Devices"
altera files
2014-03-21 19:13:50 +00:00
set_module_property DISPLAY_NAME axi_dmac
set_module_property ELABORATION_CALLBACK axi_dmac_elaborate
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
set_module_property VALIDATION_CALLBACK axi_dmac_validate
altera files
2014-03-21 19:13:50 +00:00
# files
axi_dmac: axi_dmac_hw.tcl: Use ad_ip_files helper Use the ad_ip_files helper to reduce the amount of boiler plate code. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-26 15:13:20 +00:00
ad_ip_files axi_dmac [list \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
axi_dmac: early abort support Data mover/ src axis changes Request rewind ID if TLAST received during non-last burst Consume (ignore) descriptors until last segment received Block descriptors towards destination until last segment received Request generator changes Rewind the burst ID if rewind request received Consume (ignore) descriptors until last segment received If TLAST happened on last segment replay next transfer (in progress or completed) with the adjusted ID Create completion requests for ignored segments Response generator changes Track requests Complete segments which got ignored
2018-08-25 04:57:20 +00:00
$ad_hdl_dir/library/util_cdc/sync_event.v \
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
$ad_hdl_dir/library/util_cdc/sync_gray.v \
axi_dmac: axi_dmac_hw.tcl: Use ad_ip_files helper Use the ad_ip_files helper to reduce the amount of boiler plate code. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-26 15:13:20 +00:00
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
axi_dmac: Update IP with the new util_axis_fifo Update instantiation, false path definitions and make file.
2020-11-18 16:15:45 +00:00
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
axi_dmac: burst_memory: Add support for using asymmetric memory FPGAs support different widths for the read and write port of the block SRAM cells. The DMAC can make use of this feature when the source and destination interface have a different width to up-size/down-size the data bus. Using memory cells with asymmetric port width consumes the same amount of SRAM cells, but allows to bypass the re-size blocks inside the DMAC that are otherwise used for up- and down-sizing. This reduces overall resource usage and can improve timing. If the ratio between the destination and source port is too larger to be handled by SRAM alone the SRAM block will be configured to do partial up- or down-sizing and a resize block will be inserted to take care of the remaining up-/down-sizing. E.g. if a 256-bit interface is connected to a 32-bit interface the SRAM will be used to do an initial resizing of 256 bit to 64 bit and a resize block will be used to do the remaining resizing from 64 bit to 32 bit. Currently this feature is disabled for Intel FPGAs since Quartus does not properly infer a block RAM with different read and write port widths from the current ad_asym_mem module. Once that has been resolved support for asymmetric memories can also be enabled in the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-08 09:43:43 +00:00
$ad_hdl_dir/library/common/ad_mem_asym.v \
axi_dmac: renamed .h files to .vh Vivado recognises .h files as C header files, the expected extension for Verilog Header is .vh This causes issues in simulating block designs since these files won't be exported for the simulation even if they are part of the simulation fileset.
2018-06-28 11:14:14 +00:00
inc_id.vh \
resp.vh \
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
axi_dmac_burst_memory.v \
axi_dmac: Split register map into separate sub-module Split the register map code into a separate sub-module instead of having it as part of the top-level axi_dmac.v file. This makes it easier to component test the register map behavior independently from the DMA transfer logic. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
axi_dmac_regmap.v \
axi_dmac_regmap_request.v \
axi_dmac: Rework transfer shutdown The DMAC allows a transfer to be aborted. When a transfer is aborted the DMAC shuts down as fast as possible while still completing any pending transactions as required by the protocol specifications of the port. E.g. for AXI-MM this means to complete all outstanding bursts. Once the DMAC has entered an idle state a special synchronization signal is send to all modules. This synchronization signal instructs them to flush the pipeline and remove any stale data and metadata associated with the aborted transfer. Once all data has been flushed the DMAC enters the shutdown state and is ready for the next transfer. In addition each module has a reset that resets the modules state and is used at system startup to bring them into a consistent state. Re-work the shutdown process to instead of flushing the pipeline re-use the startup reset signal also for shutdown. To manage the reset signal generation introduce the reset manager module. It contains a state machine that will assert the reset signals in the correct order and for the appropriate duration in case of a transfer shutdown. The reset signal is asserted in all domains until it has been asserted for at least 4 clock cycles in the slowest domain. This ensures that the reset signal is not de-asserted in the faster domains before the slower domains have had a chance to process the reset signal. In addition the reset signal is de-asserted in the opposite direction of the data flow. This ensures that the data sink is ready to receive data before the data source can start sending data. This simplifies the internal handshaking. This approach has multiple advantages. * Issuing a reset and removing all state takes less time than explicitly flushing one sample per clock cycle at a time. * It simplifies the logic in the faster clock domains at the expense of more complicated logic in the slower control clock domain. This allows for higher fMax on the data paths. * Less signals to synchronize from the control domain to the data domains The implementation of the pause mode has also slightly changed. Pause is now a simple disable of the data domains. When the transfer is resumed after a pause the data domains are re-enabled and continue at their previous state. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-21 14:02:44 +00:00
axi_dmac_reset_manager.v \
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
axi_dmac_resize_dest.v \
axi_dmac_resize_src.v \
axi_dmac: preparation work for reporting length of partial transfers Length of partial transfers are stored in a queue for SW reads. The presence of partial transfer is indicated by a status bit. The reporting can be enabled by a control bit. The progress of any transfer can be followed by a debug register.
2018-08-10 14:47:21 +00:00
axi_dmac_response_manager.v \
axi_dmac: Split transfer handling into separate sub-module Move the transfer logic, including the 2d module, into its own sub-module. This allows testing of the full transfer logic independently of the register map logic. The top-level module now only instantiates the register map and transfer module, but does not have any logic on its own. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
axi_dmac_transfer.v \
axi_dmac: axi_dmac_hw.tcl: Use ad_ip_files helper Use the ad_ip_files helper to reduce the amount of boiler plate code. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-26 15:13:20 +00:00
address_generator.v \
data_mover.v \
request_arb.v \
request_generator.v \
response_handler.v \
axi_register_slice.v \
library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer Update the file according to HDL guideline. Replace all occurrences of 2d_transfer with dmac_2d_transfer. Update axi_dmac/Makefile.
2022-03-31 11:33:10 +00:00
dmac_2d_transfer.v \
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
dmac_sg.v \
axi_dmac: axi_dmac_hw.tcl: Use ad_ip_files helper Use the ad_ip_files helper to reduce the amount of boiler plate code. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-26 15:13:20 +00:00
dest_axi_mm.v \
dest_axi_stream.v \
dest_fifo_inf.v \
src_axi_mm.v \
src_axi_stream.v \
src_fifo_inf.v \
splitter.v \
response_generator.v \
axi_dmac.v \
axi_dmac_constr.sdc \
]
altera files
2014-03-21 19:13:50 +00:00
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 06:01:40 +00:00
# Disable dual-clock RAM read-during-write behaviour warning.
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
set_qip_strings { "set_instance_assignment -name MESSAGE_DISABLE 276027 -entity axi_dmac_burst_memory" }
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 06:01:40 +00:00
altera files
2014-03-21 19:13:50 +00:00
# parameters
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set group "General Configuration"
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
add_parameter ID INTEGER 0
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property ID DISPLAY_NAME "Core ID"
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_parameter_property ID HDL_PARAMETER true
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property ID GROUP $group
altera files
2014-03-21 19:13:50 +00:00
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
add_parameter DMA_LENGTH_WIDTH INTEGER 24
set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME "DMA Transfer Length Register Width"
set_parameter_property DMA_LENGTH_WIDTH UNITS Bits
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property DMA_LENGTH_WIDTH ALLOWED_RANGES {8:32}
set_parameter_property DMA_LENGTH_WIDTH GROUP $group
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: Increase default store-and-forward memory size to 8 bursts A larger store-and-forward memory provides better protection against worst case memory interface latencies by being able to store more data before over-/underflowing. Based on empirical testing it was found that using a size of 4 bursts can still result in underflows/overflows under certain conditions. These do not happen when using a size of 8 bursts. This change does not significantly increase resource consumption. Both on Intel and Xilinx the block RAM has a minimum depth of 512 entries. With a default burst length of 16 beats that allows for up to 32 bursts without requiring additional block RAM. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-29 09:04:34 +00:00
add_parameter FIFO_SIZE INTEGER 8
axi_dmac: Use a more descriptive label for the store-and-forward memory size The label for the store-and-forward memory size configuration option at the moment is just "FIFO Size" and while the store-and-forward memory uses a FIFO that is just a implementation detail. Change the label to "Store-and-Forward Memory Size". This is more descriptive as it references the function not the implementation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-30 07:32:38 +00:00
set_parameter_property FIFO_SIZE DISPLAY_NAME "Store-and-Forward Memory Size (In Bursts)"
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property FIFO_SIZE HDL_PARAMETER true
axi_dmac: List valid store-and-forward memory sizes For correct operation the store-and-forward memory size must be a power-of-two in the range of 2 to 32. This is simple enough so we can list all values and let the IP Integrator and QSYS perform proper validation of the parameter. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-30 07:27:59 +00:00
set_parameter_property FIFO_SIZE ALLOWED_RANGES {2 4 8 16 32}
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property FIFO_SIZE GROUP $group
axi_dmac: Added MAX_BYTES_PER_BURST and DISABLE_DEBUG_REGISTERS parameters to Intel IP
2018-03-01 16:21:17 +00:00
add_parameter MAX_BYTES_PER_BURST INTEGER 128
set_parameter_property MAX_BYTES_PER_BURST DISPLAY_NAME "Maximum bytes per burst"
set_parameter_property MAX_BYTES_PER_BURST HDL_PARAMETER true
set_parameter_property MAX_BYTES_PER_BURST GROUP $group
axi_dmac: Add suport for 64 bit address width New improvements for the ADI DMAC IP: 1)The capability to manually overwrite the DMA_AXI_ADDR_WIDTH(from GUI or from tcl) 2)DMA_AXI_ADDR_WIDTH attribute is now visible in the Vivado GUI: -"Auto mode": Automatically calculated by the core tcl files based on the existing attached address segments. -"Manual mode": Specify the desired dma_width between 32-64 bits. 3)Added two new debug registers that return higher part of the current source/destination address. Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-09-14 11:28:34 +00:00
add_parameter DMA_AXI_ADDR_WIDTH INTEGER 32
set_parameter_property DMA_AXI_ADDR_WIDTH DISPLAY_NAME "DMA AXI Address Width"
set_parameter_property DMA_AXI_ADDR_WIDTH UNITS Bits
set_parameter_property DMA_AXI_ADDR_WIDTH HDL_PARAMETER true
set_parameter_property DMA_AXI_ADDR_WIDTH ALLOWED_RANGES {16:64}
set_parameter_property DMA_AXI_ADDR_WIDTH GROUP $group
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
foreach {suffix group} { \
"SRC" "Source" \
"DEST" "Destination" \
} {
add_display_item "Endpoint Configuration" $group "group"
add_parameter DMA_TYPE_$suffix INTEGER 0
set_parameter_property DMA_TYPE_$suffix DISPLAY_NAME "Type"
set_parameter_property DMA_TYPE_$suffix HDL_PARAMETER true
set_parameter_property DMA_TYPE_$suffix ALLOWED_RANGES \
{ "0:Memory-Mapped AXI" "1:Streaming AXI" "2:FIFO Interface" }
set_parameter_property DMA_TYPE_$suffix GROUP $group
axi_dmac: Use AXI3 for DMAC in Intel projects The buffers inside the interconnect are sized based on maximum burst sizes the masters can produce. For AXI4 the max burst size is 128 but for these projects for the default burst size of 128 bytes the DMACs are creating only burst of 8 or 16 beats depending on the bus width (128bits and 64 bits respectively). These burst sizes can fit in the AXI3 protocol where the max burst length is 16. Therefore the interconnect will be reduced. The observed reduction is around 4 Mb of block RAM per project. Another benefit is a better timing closure, since these buffers reside in the DDR3 clock domain.
2018-08-20 07:55:08 +00:00
add_parameter DMA_AXI_PROTOCOL_$suffix INTEGER 1
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
set_parameter_property DMA_AXI_PROTOCOL_$suffix DISPLAY_NAME "AXI Protocol"
set_parameter_property DMA_AXI_PROTOCOL_$suffix HDL_PARAMETER true
set_parameter_property DMA_AXI_PROTOCOL_$suffix ALLOWED_RANGES { "0:AXI4" "1:AXI3" }
set_parameter_property DMA_AXI_PROTOCOL_$suffix GROUP $group
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
add_parameter DMA_DATA_WIDTH_$suffix INTEGER 64
set_parameter_property DMA_DATA_WIDTH_$suffix DISPLAY_NAME "Bus Width"
set_parameter_property DMA_DATA_WIDTH_$suffix UNITS Bits
set_parameter_property DMA_DATA_WIDTH_$suffix HDL_PARAMETER true
set_parameter_property DMA_DATA_WIDTH_$suffix ALLOWED_RANGES {16 32 64 128 256 512 1024}
set_parameter_property DMA_DATA_WIDTH_$suffix GROUP $group
add_parameter AXI_SLICE_$suffix INTEGER 0
set_parameter_property AXI_SLICE_$suffix DISPLAY_NAME "Insert Register Slice"
set_parameter_property AXI_SLICE_$suffix DISPLAY_HINT boolean
set_parameter_property AXI_SLICE_$suffix HDL_PARAMETER true
set_parameter_property AXI_SLICE_$suffix GROUP $group
}
# FIFO interface
set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
# Scatter-Gather interface
add_parameter DMA_AXI_PROTOCOL_SG INTEGER 1
set_parameter_property DMA_AXI_PROTOCOL_SG DISPLAY_NAME "AXI Protocol"
set_parameter_property DMA_AXI_PROTOCOL_SG HDL_PARAMETER true
set_parameter_property DMA_AXI_PROTOCOL_SG ALLOWED_RANGES { "0:AXI4" "1:AXI3" }
set_parameter_property DMA_AXI_PROTOCOL_SG VISIBLE true
set_parameter_property DMA_AXI_PROTOCOL_SG GROUP $group
add_parameter DMA_DATA_WIDTH_SG INTEGER 64
set_parameter_property DMA_DATA_WIDTH_SG DISPLAY_NAME "Bus Width"
set_parameter_property DMA_DATA_WIDTH_SG UNITS Bits
set_parameter_property DMA_DATA_WIDTH_SG HDL_PARAMETER true
set_parameter_property DMA_DATA_WIDTH_SG ALLOWED_RANGES {64}
set_parameter_property DMA_DATA_WIDTH_SG VISIBLE true
set_parameter_property DMA_DATA_WIDTH_SG GROUP $group
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set group "Features"
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
add_parameter CYCLIC INTEGER 1
set_parameter_property CYCLIC DISPLAY_NAME "Cyclic Transfer Support"
set_parameter_property CYCLIC DISPLAY_HINT boolean
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_parameter_property CYCLIC HDL_PARAMETER true
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property CYCLIC GROUP $group
altera files
2014-03-21 19:13:50 +00:00
axi_dmac: Disable 2D transfer support by default The primary use-case of the DMA controller is in non-2D mode. Make this the default, since allows projects to instantiate the controller with the default configuration without having to explicitly disable 2D support. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-10-17 13:22:48 +00:00
add_parameter DMA_2D_TRANSFER INTEGER 0
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
set_parameter_property DMA_2D_TRANSFER GROUP $group
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
add_parameter DMA_SG_TRANSFER INTEGER 0
set_parameter_property DMA_SG_TRANSFER DISPLAY_NAME "SG Transfer Support"
set_parameter_property DMA_SG_TRANSFER DISPLAY_HINT boolean
set_parameter_property DMA_SG_TRANSFER HDL_PARAMETER true
set_parameter_property DMA_SG_TRANSFER GROUP $group
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
add_parameter SYNC_TRANSFER_START INTEGER 0
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support"
set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property SYNC_TRANSFER_START GROUP $group
set group "Clock Domain Configuration"
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
add_parameter AUTO_ASYNC_CLK BOOLEAN 1
set_parameter_property AUTO_ASYNC_CLK DISPLAY_NAME "Automatically Detect Clock Domains"
set_parameter_property AUTO_ASYNC_CLK HDL_PARAMETER false
set_parameter_property AUTO_ASYNC_CLK GROUP $group
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
foreach {p name} { \
ASYNC_CLK_REQ_SRC "Request and Source" \
ASYNC_CLK_SRC_DEST "Source and Destination" \
ASYNC_CLK_DEST_REQ "Destination and Request" \
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
ASYNC_CLK_REQ_SG "Request and Scatter-Gather" \
ASYNC_CLK_SRC_SG "Source and Scatter-Gather" \
ASYNC_CLK_DEST_SG "Destination and Scatter-Gather" \
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
} {
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
add_parameter ${p}_MANUAL INTEGER 1
set_parameter_property ${p}_MANUAL DISPLAY_NAME [concat $name "Clock Asynchronous"]
set_parameter_property ${p}_MANUAL DISPLAY_HINT boolean
set_parameter_property ${p}_MANUAL HDL_PARAMETER false
set_parameter_property ${p}_MANUAL VISIBLE false
set_parameter_property ${p}_MANUAL GROUP $group
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
add_parameter $p INTEGER 1
set_parameter_property $p DISPLAY_NAME [concat $name "Clock Asynchronous"]
set_parameter_property $p DISPLAY_HINT boolean
set_parameter_property $p HDL_PARAMETER true
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
set_parameter_property $p DERIVED true
set_parameter_property $p GROUP $group
}
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
add_parameter CLK_DOMAIN_REQ INTEGER
set_parameter_property CLK_DOMAIN_REQ HDL_PARAMETER false
set_parameter_property CLK_DOMAIN_REQ SYSTEM_INFO {CLOCK_DOMAIN s_axi_clock}
set_parameter_property CLK_DOMAIN_REQ VISIBLE false
set_parameter_property CLK_DOMAIN_REQ GROUP $group
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
set src_clks { \
{CLK_DOMAIN_SRC_AXI m_src_axi_clock} \
{CLK_DOMAIN_SRC_SAXI if_s_axis_aclk} \
{CLK_DOMAIN_SRC_FIFO if_fifo_wr_clk} \
}
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
set dest_clks { \
{CLK_DOMAIN_DEST_AXI m_dest_axi_clock} \
{CLK_DOMAIN_DEST_SAXI if_m_axis_aclk} \
{CLK_DOMAIN_DEST_FIFO if_fifo_rd_clk} \
}
foreach domain [list {*}$src_clks {*}$dest_clks] {
lassign $domain p clk
add_parameter $p INTEGER
set_parameter_property $p HDL_PARAMETER false
set_parameter_property $p SYSTEM_INFO [list CLOCK_DOMAIN $clk]
set_parameter_property $p VISIBLE false
axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters Group configuration parameters by function, provide human readable labels as well as specify the allowed ranges for each parameter. This prevents accidental misconfiguration and also makes it easier to inspect (or change) the configuration in the Qsys GUI. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 15:58:50 +00:00
set_parameter_property $p GROUP $group
}
axi_dmac: Added C_FIFO_SIZE parameter
2015-07-24 12:30:10 +00:00
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
add_parameter CLK_DOMAIN_SG INTEGER
set_parameter_property CLK_DOMAIN_SG HDL_PARAMETER false
set_parameter_property CLK_DOMAIN_SG SYSTEM_INFO {CLOCK_DOMAIN m_sg_axi_clock}
set_parameter_property CLK_DOMAIN_SG VISIBLE false
set_parameter_property CLK_DOMAIN_SG GROUP $group
altera files
2014-03-21 19:13:50 +00:00
# axi4 slave
up_axi.v: fixed bus width definition fixed axi_dma_regmap.v bus width missmatch
2019-07-30 13:01:10 +00:00
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 11
altera files
2014-03-21 19:13:50 +00:00
altera-9250/dma: make id width generic
2014-04-24 18:53:09 +00:00
add_interface interrupt_sender interrupt end
axi_dmac: axi_dmac_hw.tcl: Set associated reset and addressable point for the interrupt interface Altera recommends to set those properties for better qsys integration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 14:06:35 +00:00
set_interface_property interrupt_sender associatedAddressablePoint s_axi
altera-9250/dma: make id width generic
2014-04-24 18:53:09 +00:00
set_interface_property interrupt_sender associatedClock s_axi_clock
axi_dmac: axi_dmac_hw.tcl: Set associated reset and addressable point for the interrupt interface Altera recommends to set those properties for better qsys integration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 14:06:35 +00:00
set_interface_property interrupt_sender associatedReset s_axi_reset
altera-9250/dma: make id width generic
2014-04-24 18:53:09 +00:00
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq irq Output 1
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
proc axi_dmac_validate {} {
set auto_clk [get_parameter_value AUTO_ASYNC_CLK]
set type_src [get_parameter_value DMA_TYPE_SRC]
set type_dest [get_parameter_value DMA_TYPE_DEST]
axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value The MAX_BYTES_PER_BURST option allows to configure the maximum bytes that are part of a burst. This can be an arbitrary value. At the same time there is a limit of how many bytes can be supported by the memory buses. A AXI3 interface supports a maximum of 16 beats per burst and a AXI4 interface supports a maximum of 256 beats per burst. At the moment the it is possible to specify a MAX_BYTES_PER_BURST value that exceeds what can be supported by the AXI memory-mapped bus. If that is the case undefined behavior will occur and the DMAC will function incorrectly. To avoid this make sure that the MAX_BYTES_PER_BURST value does not exceed the maximum that can be supported by the interfaces. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-23 14:49:07 +00:00
set max_burst 32768
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
if {$auto_clk == true} {
global src_clks dest_clks
set req_domain [get_parameter_value CLK_DOMAIN_REQ]
set src_domain [get_parameter_value [lindex $src_clks $type_src 0]]
set dest_domain [get_parameter_value [lindex $dest_clks $type_dest 0]]
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
set sg_domain [get_parameter_value CLK_DOMAIN_SG]
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
if {$req_domain != 0 && $req_domain == $src_domain} {
set_parameter_value ASYNC_CLK_REQ_SRC 0
} else {
set_parameter_value ASYNC_CLK_REQ_SRC 1
}
if {$src_domain != 0 && $src_domain == $dest_domain} {
set_parameter_value ASYNC_CLK_SRC_DEST 0
} else {
set_parameter_value ASYNC_CLK_SRC_DEST 1
}
if {$dest_domain != 0 && $dest_domain == $req_domain} {
set_parameter_value ASYNC_CLK_DEST_REQ 0
} else {
set_parameter_value ASYNC_CLK_DEST_REQ 1
}
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
if {$sg_domain != 0 && $sg_domain == $req_domain} {
set_parameter_value ASYNC_CLK_REQ_SG 0
} else {
set_parameter_value ASYNC_CLK_REQ_SG 1
}
if {$sg_domain != 0 && $sg_domain == $src_domain} {
set_parameter_value ASYNC_CLK_SRC_SG 0
} else {
set_parameter_value ASYNC_CLK_SRC_SG 1
}
if {$sg_domain != 0 && $sg_domain == $dest_domain} {
set_parameter_value ASYNC_CLK_DEST_SG 0
} else {
set_parameter_value ASYNC_CLK_DEST_SG 1
}
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
} else {
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
foreach p {ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ ASYNC_CLK_REQ_SG ASYNC_CLK_SRC_SG ASYNC_CLK_DEST_SG} {
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
set_parameter_value $p [get_parameter_value ${p}_MANUAL]
}
}
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
foreach p {ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ ASYNC_CLK_REQ_SG ASYNC_CLK_SRC_SG ASYNC_CLK_DEST_SG} {
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_clk ? false : true]
set_parameter_property $p VISIBLE $auto_clk
}
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
foreach suffix {SRC DEST} {
axi_dmac: axi_dmac_hw.tcl: Fix indention Fix some slight indentation issues in the axi_dmac_hw.tcl. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-06 11:22:51 +00:00
if {[get_parameter_value DMA_TYPE_$suffix] == 0} {
set show_axi_protocol true
axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value The MAX_BYTES_PER_BURST option allows to configure the maximum bytes that are part of a burst. This can be an arbitrary value. At the same time there is a limit of how many bytes can be supported by the memory buses. A AXI3 interface supports a maximum of 16 beats per burst and a AXI4 interface supports a maximum of 256 beats per burst. At the moment the it is possible to specify a MAX_BYTES_PER_BURST value that exceeds what can be supported by the AXI memory-mapped bus. If that is the case undefined behavior will occur and the DMAC will function incorrectly. To avoid this make sure that the MAX_BYTES_PER_BURST value does not exceed the maximum that can be supported by the interfaces. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-23 14:49:07 +00:00
set proto [get_parameter_value DMA_AXI_PROTOCOL_$suffix]
set width [get_parameter_value DMA_DATA_WIDTH_$suffix]
if {$proto == 0} {
set max_burst [expr min($max_burst, $width * 256 / 8)]
} else {
set max_burst [expr min($max_burst, $width * 16 / 8)]
}
axi_dmac: axi_dmac_hw.tcl: Fix indention Fix some slight indentation issues in the axi_dmac_hw.tcl. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-06 11:22:51 +00:00
} else {
set show_axi_protocol false
}
set_parameter_property DMA_AXI_PROTOCOL_$suffix VISIBLE $show_axi_protocol
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
}
axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value The MAX_BYTES_PER_BURST option allows to configure the maximum bytes that are part of a burst. This can be an arbitrary value. At the same time there is a limit of how many bytes can be supported by the memory buses. A AXI3 interface supports a maximum of 16 beats per burst and a AXI4 interface supports a maximum of 256 beats per burst. At the moment the it is possible to specify a MAX_BYTES_PER_BURST value that exceeds what can be supported by the AXI memory-mapped bus. If that is the case undefined behavior will occur and the DMAC will function incorrectly. To avoid this make sure that the MAX_BYTES_PER_BURST value does not exceed the maximum that can be supported by the interfaces. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-23 14:49:07 +00:00
set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst"
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 17:44:09 +00:00
}
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
# conditional interfaces
# axi4 destination/source
add_interface m_dest_axi_clock clock end
add_interface_port m_dest_axi_clock m_dest_axi_aclk clk Input 1
add_interface m_dest_axi_reset reset end
set_interface_property m_dest_axi_reset associatedClock m_dest_axi_clock
add_interface_port m_dest_axi_reset m_dest_axi_aresetn reset_n Input 1
add_interface m_src_axi_clock clock end
add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1
add_interface m_src_axi_reset reset end
set_interface_property m_src_axi_reset associatedClock m_src_axi_clock
add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
# axi4 scatter-gather
add_interface m_sg_axi_clock clock end
add_interface_port m_sg_axi_clock m_sg_axi_aclk clk Input 1
add_interface m_sg_axi_reset reset end
set_interface_property m_sg_axi_reset associatedClock m_sg_axi_clock
add_interface_port m_sg_axi_reset m_sg_axi_aresetn reset_n Input 1
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
# axis destination/source
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2018-08-14 13:53:45 +00:00
ad_interface clock m_axis_aclk input 1 clk
ad_interface signal m_axis_xfer_req output 1 xfer_req
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
axi_dmac: bundle AXI Stream signals into bus for Intel Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.
2019-05-13 11:35:55 +00:00
add_interface m_axis axi4stream start
set_interface_property m_axis associatedClock if_m_axis_aclk
set_interface_property m_axis associatedReset s_axi_reset
add_interface_port m_axis m_axis_valid tvalid Output 1
add_interface_port m_axis m_axis_last tlast Output 1
add_interface_port m_axis m_axis_ready tready Input 1
add_interface_port m_axis m_axis_data tdata Output DMA_DATA_WIDTH_DEST
add_interface_port m_axis m_axis_user tuser Output 1
add_interface_port m_axis m_axis_id tid Output DMA_AXIS_ID_W
add_interface_port m_axis m_axis_dest tdest Output DMA_AXIS_DEST_W
add_interface_port m_axis m_axis_strb tstrb Output DMA_DATA_WIDTH_DEST/8
add_interface_port m_axis m_axis_keep tkeep Output DMA_DATA_WIDTH_DEST/8
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2018-08-14 13:53:45 +00:00
ad_interface clock s_axis_aclk input 1 clk
ad_interface signal s_axis_xfer_req output 1 xfer_req
axi_dmac: bundle AXI Stream signals into bus for Intel Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.
2019-05-13 11:35:55 +00:00
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_s_axis_aclk
set_interface_property s_axis associatedReset s_axi_reset
add_interface_port s_axis s_axis_valid tvalid Input 1
add_interface_port s_axis s_axis_last tlast Input 1
add_interface_port s_axis s_axis_ready tready Output 1
add_interface_port s_axis s_axis_data tdata Input DMA_DATA_WIDTH_SRC
add_interface_port s_axis s_axis_user tuser Input 1
add_interface_port s_axis s_axis_id tid Input DMA_AXIS_ID_W
add_interface_port s_axis s_axis_dest tdest Input DMA_AXIS_DEST_W
add_interface_port s_axis s_axis_strb tstrb Input DMA_DATA_WIDTH_SRC/8
add_interface_port s_axis s_axis_keep tkeep Input DMA_DATA_WIDTH_SRC/8
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
# fifo destination/source
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2018-08-14 13:53:45 +00:00
ad_interface clock fifo_rd_clk input 1 clk
ad_interface signal fifo_rd_en input 1 valid
ad_interface signal fifo_rd_valid output 1 valid
ad_interface signal fifo_rd_dout output DMA_DATA_WIDTH_DEST data
ad_interface signal fifo_rd_underflow output 1 unf
ad_interface signal fifo_rd_xfer_req output 1 xfer_req
ad_interface clock fifo_wr_clk input 1 clk
ad_interface signal fifo_wr_en input 1 valid
ad_interface signal fifo_wr_din input DMA_DATA_WIDTH_SRC data
ad_interface signal fifo_wr_overflow output 1 ovf
ad_interface signal fifo_wr_sync input 1 sync
ad_interface signal fifo_wr_xfer_req output 1 xfer_req
altera files
2014-03-21 19:13:50 +00:00
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
proc add_axi_master_interface {axi_type port suffix} {
add_interface $port $axi_type start
set_interface_property $port associatedClock ${port}_clock
set_interface_property $port associatedReset ${port}_reset
set_interface_property $port readIssuingCapability 1
add_interface_port $port ${port}_awvalid awvalid Output 1
add_interface_port $port ${port}_awaddr awaddr Output 32
add_interface_port $port ${port}_awready awready Input 1
add_interface_port $port ${port}_wvalid wvalid Output 1
add_interface_port $port ${port}_wdata wdata Output DMA_DATA_WIDTH_${suffix}
add_interface_port $port ${port}_wstrb wstrb Output DMA_DATA_WIDTH_${suffix}/8
add_interface_port $port ${port}_wready wready Input 1
add_interface_port $port ${port}_bvalid bvalid Input 1
add_interface_port $port ${port}_bresp bresp Input 2
add_interface_port $port ${port}_bready bready Output 1
add_interface_port $port ${port}_arvalid arvalid Output 1
add_interface_port $port ${port}_araddr araddr Output 32
add_interface_port $port ${port}_arready arready Input 1
add_interface_port $port ${port}_rvalid rvalid Input 1
add_interface_port $port ${port}_rresp rresp Input 2
add_interface_port $port ${port}_rdata rdata Input DMA_DATA_WIDTH_${suffix}
add_interface_port $port ${port}_rready rready Output 1
add_interface_port $port ${port}_awlen awlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})"
add_interface_port $port ${port}_awsize awsize Output 3
add_interface_port $port ${port}_awburst awburst Output 2
add_interface_port $port ${port}_awcache awcache Output 4
add_interface_port $port ${port}_awprot awprot Output 3
add_interface_port $port ${port}_wlast wlast Output 1
add_interface_port $port ${port}_arlen arlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})"
add_interface_port $port ${port}_arsize arsize Output 3
add_interface_port $port ${port}_arburst arburst Output 2
add_interface_port $port ${port}_arcache arcache Output 4
add_interface_port $port ${port}_arprot arprot Output 3
cosmetics: Change Altera to Intel in comments
2018-08-14 12:48:32 +00:00
# Some signals are mandatory in Intel's implementation of AXI3
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
# awid, awlock, wid, bid, arid, arlock, rid, rlast
# Hide them in AXI4
axi_dmac: Reduce the width of ID signals to minimum Reduce the width of ID signals to avoid size mismatches in Arria 10 SoC projects where the ID width of the hard IP is 4. The width of ID that reaches the slave can be increased by the interconnect if multiple masters access the slave so we end up with mismatches. Since these signals are unused it is safe to reduce them to minimum width and let the interconnect zero-extend them as required.
2018-08-20 11:58:09 +00:00
add_interface_port $port ${port}_awid awid Output 1
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
add_interface_port $port ${port}_awlock awlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
axi_dmac: Reduce the width of ID signals to minimum Reduce the width of ID signals to avoid size mismatches in Arria 10 SoC projects where the ID width of the hard IP is 4. The width of ID that reaches the slave can be increased by the interconnect if multiple masters access the slave so we end up with mismatches. Since these signals are unused it is safe to reduce them to minimum width and let the interconnect zero-extend them as required.
2018-08-20 11:58:09 +00:00
add_interface_port $port ${port}_wid wid Output 1
add_interface_port $port ${port}_arid arid Output 1
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
add_interface_port $port ${port}_arlock arlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
axi_dmac: Reduce the width of ID signals to minimum Reduce the width of ID signals to avoid size mismatches in Arria 10 SoC projects where the ID width of the hard IP is 4. The width of ID that reaches the slave can be increased by the interconnect if multiple masters access the slave so we end up with mismatches. Since these signals are unused it is safe to reduce them to minimum width and let the interconnect zero-extend them as required.
2018-08-20 11:58:09 +00:00
add_interface_port $port ${port}_rid rid Input 1
add_interface_port $port ${port}_bid bid Input 1
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
add_interface_port $port ${port}_rlast rlast Input 1
if {$axi_type == "axi4"} {
set_port_property ${port}_awid TERMINATION true
set_port_property ${port}_awlock TERMINATION true
set_port_property ${port}_wid TERMINATION true
set_port_property ${port}_arid TERMINATION true
set_port_property ${port}_arlock TERMINATION true
set_port_property ${port}_rid TERMINATION true
set_port_property ${port}_bid TERMINATION true
axi_dmac: Hook up rlast for MM-AXI source interface For the memory-mapped AXI read interface the slave asserts rlast for the last beat in a burst. This means we don't have to count the number of beats to know when the burst is completed but instead can use rlast. This slightly reduces the amount of resources needed for the MM-AXI source module and given that the beat_counter is often the bottleneck timing wise this should also improve the timing. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-08 09:12:44 +00:00
if {$port == "m_dest_axi"} {
set_port_property ${port}_rlast TERMINATION true
}
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
}
}
altera files
2014-03-21 19:13:50 +00:00
proc axi_dmac_elaborate {} {
axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities The axi_dmac can issue up to FIFO_SIZE read and write requests in parallel. This is done in order to maximize throughput and compensate for for latency. Set the {read,write}IssuingCapability properties accordingly on the AXI master interfaces. Otherwise qsys might decide to insert bridges that artificially limit the number of requests, which in turn might affect performance. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 13:27:57 +00:00
set fifo_size [get_parameter_value FIFO_SIZE]
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
set disabled_intfs {}
altera files
2014-03-21 19:13:50 +00:00
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
# add axi3 or axi4 interface depending on user selection
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
foreach {suffix port} {SRC m_src_axi DEST m_dest_axi SG m_sg_axi} {
axi_dmac: AXI3 support on Intel qsys Exposed AXI3 interface on the Intel version of the IP for UI and feature consistency. Some of the signals that are defined as optional in the AMBA standard are marked as mandatory in Qsys in case of AXI3. Because of this such signals were added to the interface of the DMAC and driven with default values. For Xilinx in order to keep existing behavior the newly added signals are hidden from the interface. New parameters are added to define the width of the AXI transaction IDs; these are hidden from the UI; We can add them to the UI if the fixed size of the IDs will cause port incompatibility issues.
2018-04-12 11:22:06 +00:00
if {[get_parameter_value DMA_AXI_PROTOCOL_${suffix}] == 0} {
set axi_type axi4
} else {
set axi_type axi
}
add_axi_master_interface $axi_type $port $suffix
}
altera files
2014-03-21 19:13:50 +00:00
# axi4 destination/source
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
if {[get_parameter_value DMA_TYPE_DEST] == 0} {
axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities The axi_dmac can issue up to FIFO_SIZE read and write requests in parallel. This is done in order to maximize throughput and compensate for for latency. Set the {read,write}IssuingCapability properties accordingly on the AXI master interfaces. Otherwise qsys might decide to insert bridges that artificially limit the number of requests, which in turn might affect performance. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 13:27:57 +00:00
set_interface_property m_dest_axi writeIssuingCapability $fifo_size
set_interface_property m_dest_axi combinedIssuingCapability $fifo_size
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
} else {
lappend disabled_intfs m_dest_axi_clock m_dest_axi_reset m_dest_axi
altera files
2014-03-21 19:13:50 +00:00
}
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
if {[get_parameter_value DMA_TYPE_SRC] == 0} {
axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities The axi_dmac can issue up to FIFO_SIZE read and write requests in parallel. This is done in order to maximize throughput and compensate for for latency. Set the {read,write}IssuingCapability properties accordingly on the AXI master interfaces. Otherwise qsys might decide to insert bridges that artificially limit the number of requests, which in turn might affect performance. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 13:27:57 +00:00
set_interface_property m_src_axi readIssuingCapability $fifo_size
set_interface_property m_src_axi combinedIssuingCapability $fifo_size
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
} else {
lappend disabled_intfs m_src_axi_clock m_src_axi_reset m_src_axi
altera files
2014-03-21 19:13:50 +00:00
}
axi_dmac: Add support for DMA Scatter-Gather This commit introduces a different interface to submit transfers, using DMA descriptors. The structure of the DMA descriptor is as follows: struct dma_desc { u32 flags, u32 id, u64 dest_addr, u64 src_addr, u64 next_sg_addr, u32 y_len, u32 x_len, u32 src_stride, u32 dst_stride, }; The 'flags' field currently offers two control bits: - bit 0: if set, the transfer will complete after this last descriptor is processed, and the DMA core will go back to idle state; if cleared, the next DMA descriptor pointed to by 'next_sg_addr' will be loaded. - bit 1: if set, an end-of-transfer interrupt will be raised after the memory segment pointed to by this descriptor has been transferred. The 'id' field corresponds to an identifier of the descriptor. The 'dest_addr' and 'src_addr' contain the destination and source addresses to use for the transfer, respectively. The 'x_len' field contains the number of bytes to transfer, minus one. The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for 2D transfers, and should be set to zero if 2D transfers are not required. To start a transfer, the address of the first DMA descriptor must be written to register 0x47c and the HWDESC bit of CONTROL register must be set. The Scatter-Gather transfer is queued similarly to the simple transfers, by writing 1 in TRANSFER_SUBMIT. The Scatter-Gather interface has a dedicated AXI-MM bus configured for read transfers, with its own dedicated clock, which can be asynchronous. The Scatter-Gather reset is generated by the reset manager to reset the logic after completing any pending transactions on the bus. When the Scatter-Gather is enabled during runtime, the legacy cyclic functionality of the DMA is disabled. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-08-10 10:10:24 +00:00
if {[get_parameter_value DMA_SG_TRANSFER] == 1} {
set_interface_property m_sg_axi readIssuingCapability $fifo_size
set_interface_property m_sg_axi combinedIssuingCapability $fifo_size
} else {
lappend disabled_intfs m_sg_axi_clock m_sg_axi_reset m_sg_axi
}
altera files
2014-03-21 19:13:50 +00:00
# axis destination/source
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
if {[get_parameter_value DMA_TYPE_DEST] != 1} {
axi_dmac: bundle AXI Stream signals into bus for Intel Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.
2019-05-13 11:35:55 +00:00
lappend disabled_intfs if_m_axis_aclk if_m_axis_xfer_req m_axis
} else {
if {[get_parameter_value HAS_AXIS_TSTRB] == 0} {
set_port_property m_axis_strb termination true
}
if {[get_parameter_value HAS_AXIS_TKEEP] == 0} {
set_port_property m_axis_keep termination true
}
if {[get_parameter_value HAS_AXIS_TLAST] == 0} {
set_port_property m_axis_last termination true
}
if {[get_parameter_value HAS_AXIS_TID] == 0} {
set_port_property m_axis_id termination true
}
if {[get_parameter_value HAS_AXIS_TDEST] == 0} {
set_port_property m_axis_dest termination true
}
if {[get_parameter_value HAS_AXIS_TUSER] == 0} {
set_port_property m_axis_user termination true
}
altera files
2014-03-21 19:13:50 +00:00
}
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
if {[get_parameter_value DMA_TYPE_SRC] != 1} {
axi_dmac: bundle AXI Stream signals into bus for Intel Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.
2019-05-13 11:35:55 +00:00
lappend disabled_intfs if_s_axis_aclk if_s_axis_xfer_req s_axis
} else {
if {[get_parameter_value HAS_AXIS_TSTRB] == 0} {
set_port_property s_axis_strb termination true
set_port_property s_axis_strb termination_value 0xFF
}
if {[get_parameter_value HAS_AXIS_TKEEP] == 0} {
set_port_property s_axis_keep termination true
set_port_property s_axis_keep termination_value 0xFF
}
if {[get_parameter_value HAS_AXIS_TLAST] == 0} {
set_port_property s_axis_last termination true
set_port_property s_axis_last termination_value 0
}
if {[get_parameter_value HAS_AXIS_TID] == 0} {
set_port_property s_axis_id termination true
set_port_property s_axis_id termination_value 0
}
if {[get_parameter_value HAS_AXIS_TDEST] == 0} {
set_port_property s_axis_dest termination true
set_port_property s_axis_dest termination_value 0
}
if {[get_parameter_value HAS_AXIS_TUSER] == 0} {
if {[get_parameter_value SYNC_TRANSFER_START] == 0} {
set_port_property s_axis_user termination true
set_port_property s_axis_user termination_value 0
}
}
axi_dmac: Control s_axis_user/fifo_wr_sync validity The ports s_axis_user or fifo_wr_sync will be active just if the SYNC_TRANSFER_START is enabled.
2017-10-02 17:15:06 +00:00
}
altera files
2014-03-21 19:13:50 +00:00
# fifo destination/source
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
if {[get_parameter_value DMA_TYPE_DEST] != 2} {
lappend disabled_intfs \
if_fifo_rd_clk if_fifo_rd_en if_fifo_rd_valid if_fifo_rd_dout \
if_fifo_rd_underflow if_fifo_rd_xfer_req
}
if {[get_parameter_value DMA_TYPE_SRC] != 2} {
lappend disabled_intfs \
if_fifo_wr_clk if_fifo_wr_en if_fifo_wr_din if_fifo_wr_overflow \
if_fifo_wr_sync if_fifo_wr_xfer_req
altera files
2014-03-21 19:13:50 +00:00
}
axi_dmac: Control s_axis_user/fifo_wr_sync validity The ports s_axis_user or fifo_wr_sync will be active just if the SYNC_TRANSFER_START is enabled.
2017-10-02 17:15:06 +00:00
if {[get_parameter_value DMA_TYPE_SRC] == 2 &&
[get_parameter_value SYNC_TRANSFER_START] == 0} {
set_port_property fifo_wr_sync termination true
set_port_property fifo_wr_sync termination_value 1
}
axi_dmac: diagnostic interface in bursts This change adds a diagnostic interface to the DMAC core. The interface exposes internal information about the core, information which can't be exposed through AXI registers due the latency and update rate. Such information is the fullness of the internal buffer. For this is exposed in bursts and is driven from the destination clock domain, as this is reflected in its name. The signal has a fixed size and is dimensioned by taking in account the supported maximum number of bursts of 128.
2018-06-07 13:20:27 +00:00
if {[get_parameter_value ENABLE_DIAGNOSTICS_IF] != 1} {
lappend disabled_intfs diagnostics_if
}
axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them Currently the axi_dmac_hw.tcl script does not create interfaces if they are not used in the current configuration. This has the disadvantage that the ports belonging to these interfaces are not included in the generated HDL wrapper. Which will generate a fair bunch of warnings when synthesizing the HDL. Instead always generate all interfaces, but disable those that are not used in the current configuration. This will make sure that the ports belonging to these interfaces are properly tied-off in the generate wrapper HDL. This reduces the amount of false positive warnings generated and makes it easier to spot actual issues. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-31 13:01:10 +00:00
foreach intf $disabled_intfs {
set_interface_property $intf ENABLED false
altera files
2014-03-21 19:13:50 +00:00
}
}
axi_dmac: Added MAX_BYTES_PER_BURST and DISABLE_DEBUG_REGISTERS parameters to Intel IP
2018-03-01 16:21:17 +00:00
set group "Debug"
add_parameter DISABLE_DEBUG_REGISTERS INTEGER 0
set_parameter_property DISABLE_DEBUG_REGISTERS DISPLAY_NAME "Disable debug registers"
set_parameter_property DISABLE_DEBUG_REGISTERS DISPLAY_HINT boolean
set_parameter_property DISABLE_DEBUG_REGISTERS HDL_PARAMETER false
set_parameter_property DISABLE_DEBUG_REGISTERS GROUP $group
axi_dmac: diagnostic interface in bursts This change adds a diagnostic interface to the DMAC core. The interface exposes internal information about the core, information which can't be exposed through AXI registers due the latency and update rate. Such information is the fullness of the internal buffer. For this is exposed in bursts and is driven from the destination clock domain, as this is reflected in its name. The signal has a fixed size and is dimensioned by taking in account the supported maximum number of bursts of 128.
2018-06-07 13:20:27 +00:00
add_parameter ENABLE_DIAGNOSTICS_IF INTEGER 0
set_parameter_property ENABLE_DIAGNOSTICS_IF DISPLAY_NAME "Enable Diagnostics Interface"
set_parameter_property ENABLE_DIAGNOSTICS_IF DISPLAY_HINT boolean
set_parameter_property ENABLE_DIAGNOSTICS_IF HDL_PARAMETER true
set_parameter_property ENABLE_DIAGNOSTICS_IF GROUP $group
add_interface diagnostics_if conduit end
add_interface_port diagnostics_if dest_diag_level_bursts dest_diag_level_bursts Output "8"
axi_dmac: bundle AXI Stream signals into bus for Intel Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.
2019-05-13 11:35:55 +00:00
set group "AXI Stream interface common configuration"
add_parameter HAS_AXIS_TSTRB INTEGER 0
set_parameter_property HAS_AXIS_TSTRB DISPLAY_NAME "AXI Stream interface has TSTRB"
set_parameter_property HAS_AXIS_TSTRB DISPLAY_HINT boolean
set_parameter_property HAS_AXIS_TSTRB HDL_PARAMETER false
set_parameter_property HAS_AXIS_TSTRB GROUP $group
add_parameter HAS_AXIS_TKEEP INTEGER 0
set_parameter_property HAS_AXIS_TKEEP DISPLAY_NAME "AXI Stream interface has TKEEP"
set_parameter_property HAS_AXIS_TKEEP DISPLAY_HINT boolean
set_parameter_property HAS_AXIS_TKEEP HDL_PARAMETER false
set_parameter_property HAS_AXIS_TKEEP GROUP $group
add_parameter HAS_AXIS_TLAST INTEGER 0
set_parameter_property HAS_AXIS_TLAST DISPLAY_NAME "AXI Stream interface has TLAST"
set_parameter_property HAS_AXIS_TLAST DISPLAY_HINT boolean
set_parameter_property HAS_AXIS_TLAST HDL_PARAMETER false
set_parameter_property HAS_AXIS_TLAST GROUP $group
add_parameter HAS_AXIS_TID INTEGER 0
set_parameter_property HAS_AXIS_TID DISPLAY_NAME "AXI Stream interface has TID"
set_parameter_property HAS_AXIS_TID DISPLAY_HINT boolean
set_parameter_property HAS_AXIS_TID HDL_PARAMETER false
set_parameter_property HAS_AXIS_TID GROUP $group
add_parameter DMA_AXIS_ID_W INTEGER 8
set_parameter_property DMA_AXIS_ID_W DISPLAY_NAME "AXI Stream TID width"
set_parameter_property DMA_AXIS_ID_W HDL_PARAMETER true
set_parameter_property DMA_AXIS_ID_W GROUP $group
add_parameter HAS_AXIS_TDEST INTEGER 0
set_parameter_property HAS_AXIS_TDEST DISPLAY_NAME "AXI Stream interface has TDEST"
set_parameter_property HAS_AXIS_TDEST DISPLAY_HINT boolean
set_parameter_property HAS_AXIS_TDEST HDL_PARAMETER false
set_parameter_property HAS_AXIS_TDEST GROUP $group
add_parameter DMA_AXIS_DEST_W INTEGER 4
set_parameter_property DMA_AXIS_DEST_W DISPLAY_NAME "AXI Stream TDEST width"
set_parameter_property DMA_AXIS_DEST_W HDL_PARAMETER true
set_parameter_property DMA_AXIS_DEST_W GROUP $group
add_parameter HAS_AXIS_TUSER INTEGER 0
set_parameter_property HAS_AXIS_TUSER DISPLAY_NAME "AXI Stream interface has TUSER"
set_parameter_property HAS_AXIS_TUSER DISPLAY_HINT boolean
set_parameter_property HAS_AXIS_TUSER HDL_PARAMETER false
set_parameter_property HAS_AXIS_TUSER GROUP $group