2017-01-31 14:43:40 +00:00
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source ../../common/zed/zed_system_bd.tcl
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source ../common/m2k_bd.tcl
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2017-04-19 13:47:21 +00:00
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# Use the 100 MHz clock for video DMA, the AXI interface clock is to slow for
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# this in this project.
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set video_dma_clocks [list \
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axi_hp0_interconnect/ACLK \
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axi_hp0_interconnect/M00_ACLK \
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axi_hp0_interconnect/S00_ACLK \
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sys_ps7/S_AXI_HP0_ACLK \
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axi_hdmi_dma/m_axi_mm2s_aclk \
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axi_hdmi_dma/m_axis_mm2s_aclk \
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axi_hdmi_core/vdma_clk
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]
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set video_dma_resets [list \
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axi_hp0_interconnect/ARESETN \
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axi_hp0_interconnect/M00_ARESETN \
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axi_hp0_interconnect/S00_ARESETN \
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]
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 100.0
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m2k: zed: Fix default HDMI clock frequency
The input clock frequency of the axi_clkgen was changed from 200 MHz to
100 Mhz. Update the divider settings accordingly to keep the standard
default output frequency of 148.5 MHz.
The incorrect divider settings did not affect operation of the design since
software reprograms them at startup anyway, but changing them avoids the
following warning:
[DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm. The computed FVCO is 445.455 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 49.000, CLKIN1_PERIOD = 10.00000, and DIVCLK_DIVIDE = 11 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
This violation may be corrected by:
1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run. Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.
4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 17:22:29 +00:00
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ad_ip_parameter axi_hdmi_clkgen CONFIG.VCO_DIV 4
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ad_ip_parameter axi_hdmi_clkgen CONFIG.VCO_MUL 37.125
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ad_ip_parameter axi_hdmi_clkgen CONFIG.CLK0_DIV 6.250
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2017-04-19 13:47:21 +00:00
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ad_ip_instance proc_sys_reset video_dma_reset
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ad_connect sys_ps7/FCLK_CLK1 video_dma_reset/slowest_sync_clk
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ad_connect sys_rstgen/peripheral_aresetn video_dma_reset/ext_reset_in
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foreach clk $video_dma_clocks {
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ad_disconnect /sys_cpu_clk $clk
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ad_connect $clk sys_ps7/FCLK_CLK1
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}
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foreach rst $video_dma_resets {
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ad_disconnect /sys_cpu_resetn $rst
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ad_connect $rst video_dma_reset/peripheral_aresetn
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}
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